PIC16C9XX
FIGURE 12-6: FLOWCHART OF A/D OPERATION
ADON = 0
Yes
ADON = 0?
No
Acquire
Selected Channel
Yes
GO = 0?
No
Yes
A/D Clock
= RC?
No
Start of A/D
Conversion Delayed
1 Instruction Cycle
Yes
Device in
SLEEP?
No
Finish Conversion
GO = 0
ADIF = 1
Abort Conversion
GO = 0
ADIF = 0
SLEEP
Power-down A/D
SLEEP Yes
Instruction?
No
Finish Conversion
GO = 0
ADIF = 1
Wait 2 TAD
Finish Conversion
GO = 0
ADIF = 1
Wake-up Yes
From Sleep?
No
Stay in Sleep
Power-down A/D
Wait 2 TAD
Wait 2 TAD
TABLE 12-2: SUMMARY OF A/D REGISTERS
Address Name
Bit 7 Bit 6 Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
Power-on
Reset
0Bh, 8Bh, INTCON
GIE
PEIE T0IE
10Bh, 18Bh
INTE
RBIE
T0IF
INTF
RBIF 0000 000x
0Ch
PIR1
LCDIF ADIF
—
—
SSPIF CCP1IF TMR2IF TMR1IF 00-- 0000
8Ch
PIE1
LCDIE ADIE
—
—
SSPIE CCP1IE TMR2IE TMR1IE 00-- 0000
1Eh
ADRES A/D Result Register
xxxx xxxx
1Fh
ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE
(1)
ADON 0000 0000
9Fh
ADCON1
—
—
—
—
—
PCFG2 PCFG1 PCFG0 ---- -000
05h
PORTA
—
—
RA5
RA4
RA3
RA2
RA1
RA0 --0x 0000
85h
TRISA
—
— PORTA Data Direction Control Register
--11 1111
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used for A/D conversion.
Note 1: Bit1 of ADCON0 is reserved, always maintain this bit clear.
Value on all
other Resets
0000 000u
00-- 0000
00-- 0000
uuuu uuuu
0000 0000
---- -000
--0u 0000
--11 1111
DS30444E - page 88
© 1997 Microchip Technology Inc.