JS48F4400PCZ00 View Datasheet(PDF) - Numonyx -> Micron
Part Name
Description
Manufacturer
JS48F4400PCZ00 Datasheet PDF : 102 Pages
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Numonyx™ Wireless Flash Memory (W18)
4.2
Signal Descriptions
Table 7 describes the signals used on the VF BGA package. Table 8 describes the
signals used on the QUAD+ package.
Table 7: Signal Descriptions - VF BGA Package
Symbol
A[22:0]
D[15:0]
ADV#
CE#
CLK
OE#
RST#
WAIT
WE#
WP#
VPP
VCC
VCCQ
VSS
VSSQ
DU
NC
Type
Name and Function
Input
Input/
Output
Input
Input
Input
Input
Input
Output
Input
Input
Power
Power
Power
Power
Power
—
—
ADDRESS INPUTS: For memory addresses. 32-Mbit: A[20:0]; 64-Mbit: A[21:0]; 128-Mbit: A[22:0]
DATA INPUTS/OUTPUTS: Inputs data and commands during write cycles; outputs data during
memory, Status Register, protection register, and configuration code reads. Data pins float when the
chip or outputs are deselected. Data is internally latched during writes.
ADDRESS VALID: ADV# indicates valid address presence on address inputs. During synchronous
read operations, all addresses are latched on ADV#’s rising edge or the next valid CLK edge with
ADV# low, whichever occurs first.
CHIP ENABLE: Asserting CE# activates internal control logic, I/O buffers, decoders, and sense amps.
De-asserting CE# deselects the device, places it in standby mode, and places all outputs in High-Z.
CLOCK: CLK synchronizes the device to the system bus frequency during synchronous reads and
increments an internal address generator. During synchronous read operations, addresses are latched
on ADV#’s rising edge or the next valid CLK edge with ADV# low, whichever occurs first.
OUTPUT ENABLE: When asserted, OE# enables the device’s output data buffers during a read cycle.
When OE# is deasserted, data outputs are placed in a high-impedance state.
RESET: When low, RST# resets internal automation and inhibits write operations. This provides data
protection during power transitions. de-asserting RST# enables normal operation and places the
device in asynchronous read-array mode.
WAIT: The WAIT signal indicates valid data during synchronous read modes. It can be configured to
be asserted-high or asserted-low based on bit 10 of the Read Configuration Register. WAIT is tri-stated
if CE# is deasserted. WAIT is not gated by OE#.
WRITE ENABLE: WE# controls writes to the CUI and array. Addresses and data are latched on the
rising edge of WE#.
WRITE PROTECT: Disables/enables the lock-down function. When WP# is asserted, the lock-down
mechanism is enabled and blocks marked lock-down cannot be unlocked through software. See
Section 13.1, “Block Lock Operations” on page 71 for details on block locking.
ERASE AND PROGRAM POWER: A valid voltage on this pin allows erasing or programming. Memory
contents cannot be altered when VPP ≤ VPPLK. Block erase and program at invalid VPP voltages should
not be attempted.
Set VPP = VCC for in-system program and erase operations. To accommodate resistor or diode drops
from the system supply, the VIH level of VPP can be as low as VPP1 min. VPP must remain above VPP1
min to perform in-system flash modification. VPP may be 0 V during read operations.
VPP2 can be applied to main blocks for 1000 cycles maximum and to parameter blocks for 2500 cycles.
VPP can be connected to 12 V for a cumulative total not to exceed 80 hours. Extended use of this pin
at 12 V may reduce block cycling capability.
DEVICE POWER SUPPLY: Writes are inhibited at VCC ≤ VLKO. Device operations at invalid VCC
voltages should not be attempted.
OUTPUT POWER SUPPLY: Enables all outputs to be driven at VCCQ. This input may be tied directly to
VCC.
GROUND: Pins for all internal device circuitry must be connected to system ground.
OUTPUT GROUND: Provides ground to all outputs which are driven by VCCQ. This signal may be tied
directly to VSS.
DO NOT USE: Do not use this pin. This pin should not be connected to any power supplies, signals or
other pins and must be floated.
NO CONNECT: No internal connection; can be driven or floated.
Datasheet
18
November 2007
Order Number: 290701-18
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