JS48F4400PCZ00 View Datasheet(PDF) - Numonyx -> Micron
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JS48F4400PCZ00 Datasheet PDF : 102 Pages
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Numonyx™ Wireless Flash Memory (W18)
Table 15: AC Write Characteristics — 90 nm (Sheet 2 of 2)
#
Sym
Parameter (1,2)
VCCQ =
1.7 V – 1.95 V
Min
Max
Unit Notes
W13
tBHWH (tBHEH)
WP# Setup to WE# (CE#) High
200
-
ns
3
W14
tWHGL (tEHGL)
Write Recovery before Read
0
-
ns
W16
tWHQV
WE# High to Valid Data
tAVQV +20
-
ns
3,6,10
W18
tWHAV
WE# High to Address Valid
0
-
ns
3,9,10
W19
tWHCV
WE# High to CLK Valid
12
-
ns
3,10
W20
tWHVH
WE# High to ADV# High
12
-
ns
3,10
W21
tVHWL
ADV# High to WE# Low
<21
ns
11
W22
tCHWL
CLK to WE# Low
<21
ns
11
W27
tWHEL
WE# High to CE# Low
0
W28
tWHVL
WE# High to ADV# Low
0
Notes:
1.
Write timing characteristics during erase suspend are the same as during write-only operations.
2.
A write operation can be terminated with either CE# or WE#.
3.
Sampled, not 100% tested.
4.
Write pulse width low (tWLWH or tELEH) is defined from CE# or WE# low (whichever occurs last) to CE# or WE# high
(whichever occurs first). Hence, tWLWH = tELEH = tWLEH = tELWH.
5.
Write pulse width high (tWHWL or tEHEL) is defined from CE# or WE# high (whichever is first) to CE# or WE# low
(whichever is last). Hence, tWLWH = tEHEL = tWHEL = tEHWL.
6.
System designers should take this into account and may insert a software No-Op instruction to delay the first read after
issuing a command.
7.
For commands other than resume commands.
8.
VPP should be held at VPP1 or VPP2 until block erase or program success is determined.
9.
Applicable during asynchronous reads following a write.
10.
tWHCH/L OR tWHVH must be met when transitioning from a write cycle to a synchronous burst read. tWHCH/L and tWHVH both
refer to the address latching event (either the rising/falling clock edge or the rising ADV# edge, whichever occurs first).
11.
The specifications tVHWL and tCHWL can be ignored if there is no clock toggling during the write bus cycle.
Table 16: AC Write Characteristics — 130 nm (Sheet 1 of 2)
#
Sym
Parameter (1,2)
VCCQ =
1.7 V – 2.24 V
-60
W1
W2
W3
W4
W5
W6
W7
W8
W9
W10
W11
W12
tPHWL (tPHEL)
tELWL (tWLEL)
tWLWH (tELEH)
tDVWH (tDVEH)
tAVWH (tAVEH)
tWHEH (tEHWH)
tWHDX (tEHDX)
tWHAX (tEHAX)
tWHWL (tEHEL)
tVPWH (tVPEH)
tQVVL
tQVBL
RST# High Recovery to WE# (CE#) Low
CE# (WE#) Setup to WE# (CE#) Low
WE# (CE#) Write Pulse Width Low
Data Setup to WE# (CE#) High
Address Setup to WE# (CE#) High
CE# (WE#) Hold from WE# (CE#) High
Data Hold from WE# (CE#) High
Address Hold from WE# (CE#) High
WE# (CE#) Pulse Width High
VPP Setup to WE# (CE#) High
VPP Hold from Valid SRD
WP# Hold from Valid SRD
Min
150
0
40
40
40
0
0
0
20
200
0
0
Max
-
-
-
-
-
-
-
-
-
-
-
-
Unit
Notes
ns
3
ns
ns
4
ns
ns
ns
ns
ns
ns
5,6,7
ns
3
ns
3,8
ns
3,8
November 2007
Order Number: 290701-18
Datasheet
37
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