JS48F4400PCZ00 View Datasheet(PDF) - Numonyx -> Micron
Part Name
Description
Manufacturer
JS48F4400PCZ00 Datasheet PDF : 102 Pages
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Numonyx™ Wireless Flash Memory (W18)
9.1.5
9.1.6
9.2
Standby
De-asserting CE# deselects the device and places it in standby mode, substantially
reducing device power consumption. In standby mode, outputs are placed in a high-
impedance state independent of OE#. If deselected during a program or erase
algorithm, the device shall consume active power until the program or erase operation
completes.
Reset
The device enters a reset mode when RST# is asserted. In reset mode, internal
circuitry is turned off and outputs are placed in a high-impedance state.
After returning from reset, a time tPHQV is required until outputs are valid, and a delay
(tPHWV) is required before a write sequence can be initiated. After this wake-up
interval, normal operation is restored. The device defaults to read-array mode, the
Status Register is set to 80h, and the Configuration Register defaults to asynchronous
page-mode reads.
If RST# is asserted during an erase or program operation, the operation aborts and the
memory contents at the aborted block or address are invalid. See Figure 19, “Reset
Operations Waveforms” on page 44 for detailed information regarding reset timings.
Like any automated device, it is important to assert RST# during system reset. When
the system comes out of reset, the processor expects to read from the flash memory
array. Automated flash memories provide status information when read during program
or erase operations. If a CPU reset occurs with no flash memory reset, proper CPU
initialization may not occur because the flash memory may be providing status
information instead of array data. Numonyx flash memories allow proper CPU
initialization following a system reset through the use of the RST# input. In this
application, RST# is controlled by the same CPU reset signal.
Device Commands
The device’s on-chip WSM manages erase and program algorithms. This local CPU
(WSM) controls the device’s in-system read, program, and erase operations. Bus cycles
to or from the flash memory conform to standard microprocessor bus cycles. RST#,
CE#, OE#, WE#, and ADV# control signals dictate data flow into and out of the device.
WAIT informs the CPU of valid data during burst reads. Table 21, “Bus Operations
Summary” on page 48 summarizes bus operations.
Device operations are selected by writing specific commands into the device’s CUI.
Table 22, “Command Codes and Descriptions” on page 51 lists all possible command
codes and descriptions. Table 23, “Bus Cycle Definitions” on page 52 lists command
definitions. Because commands are partition-specific, it is important to issue write
commands within the target address range.
Datasheet
50
November 2007
Order Number: 290701-18
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