Numonyx™ Wireless Flash Memory (W18)
Figure 27: Enhanced Factory Program Flowchart
EFP Setup
Start
VPP = 12V
Unlock Block
Write 30h
Address = WA0
Write D0h
Address = WA0
EFP setup time
Read
Status Register
EFP Setup
Done?
SR[7]=1=N
Check VPP & Lock
errors (SR[3,1])
EFP Program
Read
Status Register
SR[0]=1=N Data Stream
Ready?
SR[0] =0=Y
Write Data
Address = WA0
Read
Status Register
Program
Done?
SR[0]=0=Y
N
Last
Data?
Y
Write FFFFh
Address ≠ BBA
EFP Verify
Read
Status Register
SR[0]=1=N Verify Stream
Ready?
SR[0] =0=Y
Write Data
Address = WA0
Read
Status Register
Verify
Done?
SR[0]=0=Y
N
Last
Data?
Y
Write FFFFh
Address ≠ BBA
EFP Exit
Read
Status Register
SR[7]=0=N
EFP
Exited?
SR[7]=1=Y
Full Status Check
Procedure
Operation
Complete
Exit
EFP Setup
EFP Program
EFP Verify
Bus
State
Co m men ts
Bu s
State
Co mm en ts
Bu s
State
Comments
Write
Write
Write
Unlock V = 12V
PP
Block Unlock block
EFP Data = 30h
Setup Address = WA0
EFP Data = D0h
Confirm Address = WA0
Standby
EFP setup time
Read
Status Register
EFP Check SR[7]
Standby Setup 0 = EFP ready
Done? 1 = EFP not ready
If SR[7] = 1:
Error
Check SR[3,1]
Standby Condition
Check SR[3] = 1 = VPP error
SR[1] = 1 = locked block
Read
Status Register
Data Check SR[0]
Standby Stream 0 = Ready for data
Ready? 1 = Not ready for data
W rite
(note 1)
Read
Data = Data to program
Address = WA0
Status Register
Check SR[0]
Program
Standby
0 = Program done
Done? 1 = Program not done
Last Device automatically
Standby
Data? increments address.
W rite
Exit Data = FFFFh
Program Address not within same
Phase BBA
Read
Status Register
Verify Check SR[0]
Standby Stream 0 = Ready for verify
Ready? 1 = Not ready for verify
Write
(note 2)
Read
Data = Word to verify
Address = WA0
Status Register
Check SR[0]
Standby Verify
0 = Verify done
(note 3) Done? 1 = Verify not done
Last Device automatically
Standby
Data? increments address.
Write
Exit Data = FFFFh
Verify Address not within same
Phase BBA
EFP Exit
1. WA0 = first Word Address to be programmed within the target block. The BBA (Block Base
Address) must remain constant throughout the program phase data stream; WA can be held
Read
constant at the first address location, or it can be written to sequence up through the addresses
within the block. Writing to a BBA not equal to that of the block currently being written to
Standby
terminates the EFP program phase, and instructs the device to enter the EFP verify phase.
EF P
Exited?
Status Register
Check SR[7]
0 = Exit not finished
1 = Exit completed
2. For proper verification to occur, the verify data stream must be presented to the device in the
same sequence as that of the program phase data stream. Writing to a BBA not equal tWo A
terminates the EFP verify phase, and instructs the device to exit EFP.
3. Bits that did not fully program with the single WSM pulse of the EFP program phase receive
Repeat for subsequent operations.
After EFP exit, a Full Status Check can
determine if any program error occurred.
additional program-pulse attempts during the EFP verify phase. The device will report any
program failure by setting SR[4]=1; this check can be performed during the full status check afterSee the Full Status Check procedure in the
EFP has been exited for that block, and will indicate any error within the entire data stream.
Word Program flowchart.
Datasheet
64
November 2007
Order Number: 290701-18