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JS48F4400PCZ00 View Datasheet(PDF) - Numonyx -> Micron

Part Name
Description
Manufacturer
JS48F4400PCZ00
Numonyx
Numonyx -> Micron 
JS48F4400PCZ00 Datasheet PDF : 102 Pages
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Numonyx™ Wireless Flash Memory (W18)
Table 44: Protection Register Information
Offset
P = 39h
(P + E)h
(P + E)h
(P + 10)h
(P + 11)h
(P + 12)h
Length
Description
(Optional Flash Features and Commands)
Add.
Number of Protectuib Register fields in JEDEC ID space.
1
47:
“00h” indicates that 256 protection fields are available.
Protection Field 1: Protection Description
This field describes user-available One Time Programmable (OTP)
Protection Register bytes, Some are pre-programmed with device-
unique serial numbers. Others are user-programmable. Bits are 0-15
point to the Protection Register lock byte, the section’s first byte. The
following bytes are factory pre-programmed and user-programmable:
48:
• bits 0-7 = Lock/bytes JEDEC-plane physical low
49:
4
address
4A:
• bites 8-15 = Lock/bytes JEDEC-plane physical high 4B:
address
• bits 16-23 = “n” such that 2n = factory pre-
programmed bytes
bits 24-31 = “n” such that 2n = user-programmable bytes
Hex
Code
--01
--80
--00
--03
--03
Value
1
80h
00h
8 byte
8 byte
Table 45: Burst Read Information for Non-muxed Device
Offset(1)
P = 39h
(P+13)h
(P+14)h
(P+15)h
(P+16)h
(P+17)h
(P+18)h
Length
Description
(Optional flash features and commands)
1 Page Mode Read capability
bits 0–7 = “n” such that 2n HEX value represents the number of
read-page bytes. See offset 28h for device word width to
determine page-mode data output width. 00h indicates no
read page buffer.
1 Number of synchronous mode read configuration fields that
follow. 00h indicates no burst capability.
1 Synchronous mode read capability configuration 1
Bits 3–7 = Reserved
bits 0–2 “n” such that 2n+1 HEX value represents the
maximum number of continuous synchronous reads when
the device is configured for its maximum word width. A value
of 07h indicates that the device is capable of continuous
linear bursts that will output data until the internal burst
counter reaches the end of the device’s burstable address
space. This field’s 3-bit value can be written directly to the
Read Configuration Register bits 0–2 if the device is
configured for its maximum word width. See offset 28h for
word width to determine the burst data output width.
1 Synchronous mode read capability configuration 2
1 Synchronous mode read capability configuration 3
1 Synchronous mode read capability configuration 4
Hex
Add. Code Value
4C: --03 8 byte
4D: --04 4
4E: --01 4
4F: --02 8
50: --03 16
51: --07 Cont
November 2007
Order Number: 290701-18
Datasheet
95

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