PCA85176(2010) View Datasheet(PDF) - NXP Semiconductors.
Part Name
Description
Manufacturer
PCA85176 Datasheet PDF : 44 Pages
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NXP Semiconductors
PCA85176
Universal LCD driver for low multiplex rates
Table 6. Blink frequencies[1]
Blink mode
Blink frequency equation
off
-
1
fblink
=
-f--c---l-k--
768
2
fblink
=
---f--c--l--k---
1536
3
fblink
=
---f--c--l--k---
3072
[1] The blink frequency is proportional to the clock frequency (fclk). For the range of the clock frequency see
Table 17.
The entire display can blink at a frequency other than the nominal blink frequency. This
can be effectively performed by resetting and setting the display enable bit E at the
required rate using the mode-set command (see Table 10).
7.16 Characteristics of the I2C-bus
The I2C-bus is for bidirectional, two-line communication between different ICs or modules.
The two lines are a Serial DAta Line (SDA) and a Serial Clock Line (SCL). Both lines must
be connected to a positive supply via a pull-up resistor when connected to the output
stages of a device. Data transfer may be initiated only when the bus is not busy.
7.16.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as a control signal (see Figure 12).
SDA
SCL
Fig 12. Bit transfer
data line
stable;
data valid
change
of data
allowed
mba607
7.16.2 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy.
A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the START
condition - S.
A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition - P (see Figure 13).
PCA85176_1
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 01 — 14 April 2010
© NXP B.V. 2010. All rights reserved.
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