PCA9548AD(2009) View Datasheet(PDF) - NXP Semiconductors.
Part Name
Description
Manufacturer
PCA9548AD Datasheet PDF : 26 Pages
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NXP Semiconductors
PCA9548A
8-channel I2C-bus switch with reset
11. Dynamic characteristics
Table 8.
Symbol
tPD
fSCL
tBUF
tHD;STA
tLOW
tHIGH
tSU;STA
tSU;STO
tHD;DAT
tSU;DAT
tr
tf
Cb
tSP
tVD;DAT
tVD;ACK
RESET
tw(rst)L
trst
tREC;STA
Dynamic characteristics
Parameter
Conditions
propagation delay
from SDA to SDx,
or SCL to SCx
SCL clock frequency
bus free time between a STOP and
START condition
hold time (repeated) START condition
LOW period of the SCL clock
HIGH period of the SCL clock
set-up time for a repeated START
condition
set-up time for STOP condition
data hold time
data set-up time
rise time of both SDA and SCL signals
fall time of both SDA and SCL signals
capacitive load for each bus line
pulse width of spikes that must be
suppressed by the input filter
data valid time
HIGH-to-LOW
LOW-to-HIGH
data valid acknowledge time
LOW-level reset time
reset time
recovery time to START condition
SDA clear
Standard-mode
I2C-bus
Min Max
-
0.3[1]
Fast-mode I2C-bus Unit
Min
Max
-
0.3[1] ns
0
100
4.7
-
0
400 kHz
1.3
- µs
[2] 4.0
-
4.7
-
4.0
-
4.7
-
0.6
- µs
1.3
- µs
0.6
- µs
0.6
- µs
4.0
-
0.6
- µs
0[3]
3.45
0[3]
0.9 µs
250
-
100
- ns
-
1000 20 + 0.1Cb[4] 300 ns
-
300 20 + 0.1Cb[4] 300 ns
-
400
-
400 pF
-
50
-
50 ns
[5]
-
1
[5]
-
0.6
-
1
-
1 µs
-
0.6 µs
-
1 µs
4
-
500
-
0
-
4
- ns
500
- ns
0
- ns
[1] Pass gate propagation delay is calculated from the 20 Ω typical Ron and the 15 pF load capacitance.
[2] After this period, the first clock pulse is generated.
[3] A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIH(min) of the SCL signal) in order to
bridge the undefined region of the falling edge of SCL.
[4] Cb = total capacitance of one bus line in pF.
[5] Measurements taken with 1 kΩ pull-up resistor and 50 pF load.
PCA9548A_3
Product data sheet
Rev. 03 — 7 July 2009
© NXP B.V. 2009. All rights reserved.
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