ST52T400 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
ST52T400
STMicroelectronics
ST52T400 Datasheet PDF : 94 Pages
| |||
ST52T400/T440/E440/T441
2 INTERNAL ARCHITECTURE
ST52x400/440/441 is composed of the following
blocks and peripherals:
s Control Unit (CU)
s Data Processing Unit (DPU)
s ALU
s Decision Processor (DP)
s EPROM
s 256 Byte RAM
s Clock Oscillator
s Analog Multiplexer and Analog Comparator
s 1 PWM / Timer
s 1 Triac/PWM Driver
s Digital I/O port
2.1 Control Unit and Data Processing Unit
The Control Unit (CU) formally includes five main
blocks. Each block decodes a set of instructions,
generating the appropriate control signals. The
main parts of the CU are shown in Figure 2.1.
The five different parts of the CU manage Load-
ing, Logic/Arithmetic, Jump, Control and Decision
Processor (DP) instructions sets.
The block called “Collector” manages the signals
deriving from the different parts of the CU then
defines the signals for the Data Processing Unit
(DPU) and for the different peripherals of the ICU.
The block called “Arbiter” manages the different
parts of the CU in order to have only one part of
the system activated during working mode.
The CU structure is highly flexible, designed with
the objective of easily adapting the core of the
microcontroller to market needs. New instructions
sets or new peripherals can be easily included
without changing the structure of the microcontrol-
ler, maintaining code compatibility.
The CU reads and decodifies the instructions
stored on the EPROM (Fetch). According to the
instructions type, the Arbiter activates one of the
main blocks of the CU. Afterwards, all the control
signals for the DPU are generated.
A set of 55 different arithmetic, DP and logic
instructions is available. The arithmetic instruc-
tions operate to all the RAM addresses without the
need of using special registers.
The DPU receives, stores and sends the instruc-
tions coming from the EPROM, RAM or from the
peripherals in order to execute them.
2.1.1 Program Counter.
The Program Counter (PC) is a 13-bit register that
contains the address of the next memory location
to be processed by the core. This memory loca-
tion may be an opcode, an operand or an address
of an operand.
Figure 2.1 CU Block Diagram
MicroCode
A
R
B
I
T
E
R
Loading
Instruction Set
Logic Arithmetic
Instruction Set
Jump
Instruction Set
Control
Instruction Set
C
O
L
L
E
Control
C
Signals
T
O
R
Clock Master
Decision Processor
Instruction Set
19/94
Share Link: 