ST52T400 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST52T400

8-BIT INTELLIGENT CONTROLLER UNIT (ICU) Timer/PWM, Analog Comparator, Triac/PWM Timer, WDG

STMicroelectronics 

ST52T400/T440/E440/T441

The locations 0, 1 and 2 contain the jump instruc-

tion to the first code line. This instruction is auto-

matically inserted by the Assembler tool. The

operations that can be performed on EPROM dur-

ing the Programming Phase are: Stand By, Mem-

ory Writing, Reading and Verify/Margin Mode,

Memory Lock, IDCode Writing and Verify.

The operations above are managed by using the

4-bit EPROM Control Register. The reading phase

is executed with VPP= 5V±5%, while the verify/

Margin Mode phase needs VPP= 12V±5%. The

Blank Check must be a reading operation with

VPP= 5V±5%.

Table 3.1 illustrates the EPROM Control Register

codes used to select the operation. Programming

of the EPROM Control Register is described

below.

3.1 EPROM Programming Phase Procedure

Programming mode is selected by applying

12V±5% voltage or 5V±5% voltage to the VPP pin

and setting the RESET pin =Vss

If the VPP voltage is 5V±5% only reading may be

performed.

RST_ADD (PB0), INC_ADD (PB1), RST_CONF

(PB2), INC_CONF (PB3) and PHASE (PB7) are

the control signals applied during Programming

Mode.

The signals RST_ADD, RST_CONF and PHASE

are active on level, the others are active on rising

edge.

The signals RST_ADD and PHASE are active low,

signal on RST_CONF is active high.

Data in/out digital signals are transferred through

the pins of Port A.

The memory may be locked by means of the

Memory Lock Status flag, that is used to enable

EPROM operations.

If Memory Lock Status flag is 1 all EPROM opera-

tions are enabled, otherwise, it is only possible to

read (and verify) the OTP code and the Memory

Lock Status flag.

Only If EPROM is not locked by means of Lock

Cell (see paragraph EPROM Locking), may

EPROM operations be enabled, changing the

Memory Lock Status flag from 0 to 1.

The signal RST_ADD (PB0) resets the memory

address register and the Memory Lock Status flag.

Therefore, when the RST_ADD becomes high,

the memory must be unlocked in order to read or

write.

The signal RST_CONF (PB2) resets the EPROM,

Figure 3.2 EPROM Programming Timing

DATA

DATA

DATA

PA(0:7)

DATA

OUT

DATA

IN

DATA

OUT

DATA

OUT

RST_ADD

RST_CONF

INC_ADD

INC_CONF

PHASE

100nS

10µS

MEMORY UNLOCK

MEMORY WRITING

LOCATION ADDRESS =1

MEMORY VERIFY

MARGIN MODE

34/94

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