ST7PSCR1E4M1/XXX View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST7PSCR1E4M1/XXX

8-BIT LOW-POWER, FULL-SPEED USB MCU WITH 16K FLASH, 768 RAM, SMARTCARD I/F, TIMER

STMicroelectronics 

ST7SCR

USB INTERFACE (Cont’d)

ENDPOINT 2 RECEPTION

(EP2RXR)

Read/Write

Reset value: 0000 0000 (00h)

REGISTER

7

0

0

0

0

0

CTR_R DTOG STAT_ STAT_

X _RX RX1 RX0

This register is used for controlling Endpoint 2 re-

ception. Bits 2:0 are also reset by a USB reset, ei-

ther received from the USB or forced through the

FRES bit in the USBCTLR register.

Bits [7:4] = Reserved, forced by hardware to 0.

Bit 3 = CTR_RX Reception Correct Transfer.

This bit is set by hardware when a correct transfer

operation is performed in reception. This bit must

be cleared after that the corresponding interrupt

has been serviced.

Bit 2 = DTOG_RX Data Toggle, for reception

transfers.

It contains the expected value of the toggle bit

(0=DATA0, 1=DATA1) for the next data packet.

The receiver toggles DTOG_RX only if it receives

acorrect data packet and the packet’s data PID

matches the receiver sequence bit.

Bits [1:0] = STAT_RX [1:0] Status bits, for recep-

tion transfers.

These bits contain the information about the end-

point status, which is listed below:

Table 18. Reception Status Encoding

STAT_RX1 STAT_RX0

Meaning

0

0

DISABLED: reception trans-

fers cannot be executed.

STALL: the endpoint is stalled

0

1

and all reception requests re-

sult in a STALL handshake.

NAK: the endpoint is naked

1

0

and all reception requests re-

sult in a NAK handshake.

1

1

VALID: this endpoint is ena-

bled for reception.

These bits are written by software, but hardware

sets the STAT_RX bits to NAK when a correct

transfer has occurred (CTR=1) addressed to this

endpoint, so the software has the time to examine

the received data before acknowledging a new

transaction.

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