PIC16LCR620AT-20I/SO View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC16LCR620AT-20I/SO

EPROM-Based 8-Bit CMOS Microcontrollers

Microchip Technology 

PIC16C62X

4.2.2 SPECIAL FUNCTION REGISTERS

The Special Function Registers are registers used by

the CPU and Peripheral functions for controlling the

desired operation of the device (Table 4-1). These

registers are static RAM.

The Special Function Registers can be classified into

two sets (core and peripheral). The Special Function

Registers associated with the “core” functions are

described in this section. Those related to the operation

of the peripheral features are described in the section

of that peripheral feature.

TABLE 4-1: SPECIAL REGISTERS FOR THE PIC16C62X

Address Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

POR Reset

Value on all

other

RESETS(1)

Bank 0

00h

INDF

01h

TMR0

02h

PCL

03h

STATUS

04h

FSR

05h

PORTA

06h

PORTB

07h-09h Unimplemented

0Ah

PCLATH

0Bh

INTCON

0Ch

PIR1

0Dh-1Eh Unimplemented

1Fh

CMCON

Bank 1

Addressing this location uses contents of FSR to address data memory (not a physical

register)

Timer0 Module’s Register

Program Counter's (PC) Least Significant Byte

IRP(2)

RP1(2)

RP0

TO

PD

Z

DC

C

Indirect data memory address pointer

—

—

—

RA4

RA3

RA2

RA1

RA0

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

—

—

— Write buffer for upper 5 bits of program counter

GIE

PEIE

T0IE

INTE

RBIE

T0IF

INTF

RBIF

—

CMIF

—

—

—

—

—

—

C2OUT C1OUT

—

—

CIS

CM2

CM1

CM0

xxxx xxxx

xxxx xxxx

0000 0000

0001 1xxx

xxxx xxxx

---x 0000

xxxx xxxx

—

---0 0000

0000 000x

-0-- ----

—

00-- 0000

xxxx xxxx

uuuu uuuu

0000 0000

000q quuu

uuuu uuuu

---u 0000

uuuu uuuu

—

---0 0000

0000 000u

-0-- ----

—

00-- 0000

80h

INDF

Addressing this location uses contents of FSR to address data memory (not a physical

register)

xxxx xxxx xxxx xxxx

81h

OPTION

RBPU INTEDG T0CS T0SE

PSA

PS2

PS1

PS0 1111 1111 1111 1111

82h

PCL

83h

STATUS

Program Counter's (PC) Least Significant Byte

0000 0000 0000 0000

IRP(2)

RP1(2)

RP0

TO

PD

Z

DC

C

0001 1xxx 000q quuu

84h

FSR

Indirect data memory address pointer

xxxx xxxx uuuu uuuu

85h

TRISA

—

—

—

TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 ---1 1111 ---1 1111

86h

TRISB

TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 1111 1111

87h-89h Unimplemented

—

—

8Ah

PCLATH

—

—

— Write buffer for upper 5 bits of program counter

---0 0000 ---0 0000

8Bh

INTCON

GIE

PEIE

T0IE

INTE

RBIE

T0IF

INTF

RBIF 0000 000x 0000 000u

8Ch

PIE1

—

CMIE

—

—

—

—

—

—

-0-- ---- -0-- ----

8Dh

Unimplemented

—

—

8Eh

PCON

—

—

—

—

—

—

POR

BOR ---- --0x ---- --uq

8Fh-9Eh Unimplemented

—

—

9Fh

VRCON

VREN VROE VRR

—

VR3

VR2

VR1

VR0 000- 0000 000- 0000

Legend: — = Unimplemented locations read as ‘0’, u = unchanged, x = unknown,

q = value depends on condition, shaded = unimplemented

Note 1: Other (non Power-up) Resets include MCLR Reset, Brown-out Reset and Watchdog Timer Reset during

normal operation.

2: IRP & RP1 bits are reserved; always maintain these bits clear.

 2003 Microchip Technology Inc.

DS30235J-page 17

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