PIC16LC620A-04I/JW View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC16LC620A-04I/JW

EPROM-Based 8-Bit CMOS Microcontrollers

Microchip Technology 

PIC16C62X

EXAMPLE 8-1:

VOLTAGE REFERENCE

CONFIGURATION

MOVLW

MOVWF

BSF

MOVLW

MOVWF

MOVLW

MOVWF

BCF

CALL

0x02

CMCON

STATUS,RP0

0x0F

TRISA

0xA6

VRCON

STATUS,RP0

DELAY10

; 4 Inputs Muxed

; to 2 comps.

; go to Bank 1

; RA3-RA0 are

; inputs

; enable VREF

; low range

; set VR<3:0>=6

; go to Bank 0

; 10µs delay

8.2 Voltage Reference Accuracy/Error

The full range of VSS to VDD cannot be realized due to the

construction of the module. The transistors on the top

and bottom of the resistor ladder network (Figure 8-1)

keep VREF from approaching VSS or VDD. The voltage

reference is VDD derived and therefore, the VREF output

changes with fluctuations in VDD. The tested absolute

accuracy of the voltage reference can be found in

Table 12-2.

8.3 Operation During SLEEP

8.4 Effects of a RESET

A device RESET disables the voltage reference by

clearing bit VREN (VRCON<7>). This reset also

disconnects the reference from the RA2 pin by clearing

bit VROE (VRCON<6>) and selects the high voltage

range by clearing bit VRR (VRCON<5>). The VREF

value select bits, VRCON<3:0>, are also cleared.

8.5 Connection Considerations

The voltage reference module operates independently

of the comparator module. The output of the reference

generator may be connected to the RA2 pin if the

TRISA<2> bit is set and the VROE bit, VRCON<6>, is

set. Enabling the voltage reference output onto the

RA2 pin with an input signal present will increase

current consumption. Connecting RA2 as a digital

output with VREF enabled will also increase current

consumption.

The RA2 pin can be used as a simple D/A output with

limited drive capability. Due to the limited drive

capability, a buffer must be used in conjunction with the

voltage reference output for external connections to

VREF. Figure 8-2 shows an example buffering

technique.

When the device wakes up from SLEEP through an

interrupt or a Watchdog Timer time-out, the contents of

the VRCON register are not affected. To minimize

current consumption in SLEEP mode, the voltage

reference should be disabled.

FIGURE 8-2:

VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE

VREF

Module

R(1)

Voltage

Reference

Output

Impedance

RA

•

+

–

•

VREF Output

Note 1: R is dependent upon the Voltage Reference Configuration VRCON<3:0> and VRCON<5>.

TABLE 8-1: REGISTERS ASSOCIATED WITH VOLTAGE REFERENCE

Address Name

Bit 7

Bit 6 Bit 5 Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

9Fh

1Fh

85h

Note:

VRCON VREN VROE VRR

CMCON C2OUT C1OUT —

TRISA

—

—

—

- = Unimplemented, read as "0"

—

—

TRISA4

VR3

CIS

TRISA3

VR2

CM2

TRISA2

VR1

CM1

TRISA1

VR0

CM0

TRISA0

Value On

POR

000- 0000

00-- 0000

---1 1111

Value On

All Other

RESETS

000- 0000

00-- 0000

---1 1111

DS30235J-page 44

 2003 Microchip Technology Inc.

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