ST72521AR7TC View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST72521AR7TC

8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC, FIVE TIMERS, SPI, SCI, I2C, CAN INTERFACE

STMicroelectronics 

ST72521M/R/AR

I2C BUS INTERFACE (Cont’d)

10.7.5 Low Power Modes

Mode

WAIT

HALT

Description

No effect on I2C interface.

I2C interrupts cause the device to exit from WAIT mode.

I2C registers are frozen.

In HALT mode, the I2C interface is inactive and does not acknowledge data on the bus. The I2C interface

resumes operation when the MCU is woken up by an interrupt with “exit from HALT mode” capability.

10.7.6 Interrupts

Figure 66. Event Flags and Interrupt Generation

ADD10

ITE

BTF

ADSL

SB

AF

STOPF

ARLO

BERR

*

* EVF can also be set by EV6 or an error from the SR2 register.

INTERRUPT

EVF

Interrupt Event

10-bit Address Sent Event (Master mode)

End of Byte Transfer Event

Address Matched Event (Slave mode)

Start Bit Generation Event (Master mode)

Acknowledge Failure Event

Stop Detection Event (Slave mode)

Arbitration Lost Event (Multimaster configuration)

Bus Error Event

Note: The I2C interrupt events are connected to

the same interrupt vector (see Interrupts chapter).

They generate an interrupt if the corresponding

Enable Control Bit is set and the I-bit in the CC reg-

ister is reset (RIM instruction).

Event

Flag

Enable

Control

Bit

ADD10

BTF

ADSEL

SB

ITE

AF

STOPF

ARLO

BERR

Exit

from

Wait

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Exit

from

Halt

No

No

No

No

No

No

No

No

120/199

Share Link: