ST72521R7T5 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST72521R7T5

8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC, FIVE TIMERS, SPI, SCI, I2C, CAN INTERFACE

STMicroelectronics 

ST72521M/R/AR

7.7 EXTERNAL INTERRUPT CONTROL REGISTER (EICR)

Read /Write

Reset Value: 0000 0000 (00h)

- ei0 (port A3..0)

7

0

IS11 IS10 IPB IS21 IS20 IPA TLIS TLIE

Bit 7:6 = IS1[1:0] ei2 and ei3 sensitivity

The interrupt sensitivity, defined using the IS1[1:0]

bits, is applied to the following external interrupts:

- ei2 (port B3..0)

IS21 IS20

00

01

10

11

External Interrupt Sensitivity

IPA bit =0

IPA bit =1

Falling edge &

low level

Rising edge

& high level

Rising edge only Falling edge only

Falling edge only Rising edge only

Rising and falling edge

IS11 IS10

00

01

10

11

External Interrupt Sensitivity

IPB bit =0

IPB bit =1

Falling edge &

low level

Rising edge

& high level

Rising edge only Falling edge only

Falling edge only Rising edge only

Rising and falling edge

- ei3 (port B7..4)

IS11 IS10

00

01

10

11

External Interrupt Sensitivity

Falling edge & low level

Rising edge only

Falling edge only

Rising and falling edge

These 2 bits can be written only when I1 and I0 of

the CC register are both set to 1 (level 3).

Bit 5 = IPB Interrupt polarity for port B

This bit is used to invert the sensitivity of the port B

[3:0] external interrupts. It can be set and cleared

by software only when I1 and I0 of the CC register

are both set to 1 (level 3).

0: No sensitivity inversion

1: Sensitivity inversion

- ei1 (port F2..0)

IS21 IS20

00

01

10

11

External Interrupt Sensitivity

Falling edge & low level

Rising edge only

Falling edge only

Rising and falling edge

These 2 bits can be written only when I1 and I0 of

the CC register are both set to 1 (level 3).

Bit 2 = IPA Interrupt polarity for port A

This bit is used to invert the sensitivity of the port A

[3:0] external interrupts. It can be set and cleared

by software only when I1 and I0 of the CC register

are both set to 1 (level 3).

0: No sensitivity inversion

1: Sensitivity inversion

Bit 1 = TLIS TLI sensitivity

This bit allows to toggle the TLI edge sensitivity. It

can be set and cleared by software only when

TLIE bit is cleared.

0: Falling edge

1: Rising edge

Bit 4:3 = IS2[1:0] ei0 and ei1 sensitivity

The interrupt sensitivity, defined using the IS2[1:0]

bits, is applied to the following external interrupts:

Bit 0 = TLIE TLI enable

This bit allows to enable or disable the TLI capabil-

ity on the dedicated pin. It is set and cleared by

software.

0: TLI disabled

1: TLI enabled

Note: a parasitic interrupt can be generated when

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