ST7LITE0x, ST7LITESx
13.11 8-BIT ADC CHARACTERISTICS
TA = -40°C to 85°C, unless otherwise specified
Symbol
Parameter
Conditions
Min
fADC ADC clock frequency
VAIN Conversion voltage range
VSS
RAIN External input resistor
CADC Internal sample and hold capacitor VDD=5V
tSTAB Stabilization time after ADC enable
tCONV Conversion time (tSAMPLE+tHOLD)
tSAMPLE Sample capacitor loading time
fCPU=8MHz, fADC=4MHz
4
tHOLD Hold conversion time
8
Typ
3
0 2)
3
Max
4
VDD
10 1)
Unit
MHz
V
kΩ
pF
µs
1/fADC
Notes:
1. Unless otherwise specified, typical data are based on TA=25°C and VDD-VSS=5V. They are given only as design guide-
lines and are not tested.
2. Data based on characterization results, not tested in production.
3. Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than 10kΩ). Data
based on characterization results, not tested in production.
4. The stabilization time of the AD converter is masked by the first tLOAD. The first conversion after the enable is then
always valid.
Figure 80. Typical Application with ADC
VAIN
RAIN
AINx
CAIN
VDD
VT
0.6V
VT
0.6V
2kΩ(max)
8-Bit A/D
Conversion
IL
±1µA
CADC
3pF
ST7XX
105/125