ST6285BQ1 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
ST6285BQ1 Datasheet PDF : 78 Pages
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ST62T85B/E85B
INTERRUPTS (Cont’d)
3.4.3 Interrupt Option Register (IOR)
The Interrupt Option Register (IOR) is used to en-
able/disable the individual interrupt sources and to
select the operating mode of the external interrupt
inputs. This register is write-only and cannot be
accessed by single-bit operations.
Address: 0C8h — Write Only
Reset status: 00h
7
0
- LES ESB GEN -
-
-
-
Bit 5 = ESB: Edge Selection bit.
The bit ESB selects the polarity of the interrupt
source #2.
Bit 4 = GEN: Global Enable Interrupt. When this bit
is set to one, all interrupts are enabled. When this
bit is cleared to zero all the interrupts (excluding
NMI) are disabled.
When the GEN bit is low, the NMI interrupt is ac-
tive but cannot cause a wake up from STOP/WAIT
modes.
This register is cleared on reset.
3.4.4 Interrupt sources
Bit 7, Bits 3-0 = Unused.
Interrupt sources available on the
Bit 6 = LES: Level/Edge Selection bit.
) When this bit is set to one, the interrupt source #1
t(s is level sensitive. When cleared to zero the edge
sensitive mode for interrupt request is selected.
ST62E85B/T80B are summarized in the Table 11
with associated mask bit to enable/disable the in-
terrupt request.
uc Table 11. Interrupt Requests and Mask Bits
rod Peripheral
Register
Address
Register
Mask bit
P GENERAL
IOR
C8h
GEN
TIMER 1
TSCR1
D4h
ETI
te A/D CONVERTER ADCR
D1h
EAI
le SPI
SPI
C2h
ALL
o Port PAn
ORPA-DRPA C0h-C4h
ORPAn-DRPAn
bs Port PBn
ORPB-DRPB C1h-C5h
ORPBn-DRPBn
O Port PCn
ORPC-DRPC C6h-CFh
ORPCn-DRPCn
) - ARTIMER
ARMC
E5h
OVIE
CPIE
Obsolete Product(s UART
UARTCR
D7h
RXIEN
TXIEN
Masked Interrupt Source
All Interrupts, excluding NMI
TMZ: TIMER Overflow
EOC: End of Conversion
End of Transmission
PAn pin
PBn pin
PCn pin
OVF: ARTIMER Overflow
CPF: Successful Compare
RXRDY: byte received
TXMT: byte sent
Interrupt
source
All
source 3
source 4
source 1
source 2
source 2
source 2
source 3
source 4
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