ST63T69B1 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST63T69B1

8-BIT HCMOS MCU FOR DIGITAL CONTROLLED MULTI FREQUENCY MONITOR

STMicroelectronics 

ST6369

DEDICATED LATCHES

Two latches are available which may generate in-

terrupts to the ST6369 core.

The HSYNC latch is set either by the falling or ris-

ing edge of the signal on pin PC6(HSYNC). If bit 1

(HSYEDGE) of the latches register (E9H) is high,

then the latch will be triggered on the rising edge of

the signal at PC6(HSYNC). If bit 1 (HSYEDGE) is

low, then the latch will be triggered on the falling

edge of the signal at PC6(HSYNC). The HSYNC

latch can be reset by setting bit 3 (RESHSYLAT) of

the latches register; the bit is set only and a high

should be written every time the HSYNC latch

needs to be reset. If bit 2 (HSYINTEN) of the

latches register (E9H) is high, then the output of

the HSYNC latch, HSYNCN, may generate an in-

terrupt (#0). HSYNCN is inverted with respect to

the state of the HSYNC latch. If bit 2 (HSYINTEN)

is low, then the output of the HSYNC latch,

HSYNCN, is forced high. The state of the HSYNC

latch may be read from bit 3 (HSYNC) of register

E4H; if the HSYNC latch is set, then bit 3 will be

high.

The PWR latch is set either by the falling or rising

edge of the signal on pin PC4(PWRIN). If bit 4

(PWREDGE) of the latches register (E9H) is high,

then the latch will be triggered on the rising edge of

the signal at PC4(PWRIN). If bit 4 (PWREDGE) is

low, then the latch will be triggered on the falling

edge of the signal at PC4(PWRIN). The PWR latch

can be reset by setting bit 6 (RESPWRLAT) of the

latches register; the bit is set only and a high

should be written every time the PWR latch needs

to be reset. If bit 5 (PWRINTEN) of the latches reg-

ister (E9H) is high, then the output of the PWR

latch, PWRINTN, may generate an interrupt (#4).

PWRINTN is inverted with respect to the state of

the PWR latch. If bit 5 (PWRINTEN) is low, then

the output of the PWR latch, PWRINTN, is forced

high.

Figure 55. Dedicated Latches Control Register

DLCR

Dedicated Latches Control

Registe r

(E9H, Write Only)

D7 D6 D5 D4 D3 D2 D1 D0

Unuse d

HSYEDGE

HSYINTEN

RESHSYLAT

PWREDGE

PWRINTEN

RESPWRLAT

Unuse d

D0. This bit is not used

D7. This bit is not used

RESPWRLAT. Resets the PWR latch; this bit is set

only.

PWRINTEN. This bit enables the PWRINTN signal

(#4) from the latch to the ST6369 core. Undefined

after reset.

PWREDGE. The bit determines the edge which

will cause the PWRIN latch to be set. If this bit is

high, than the PWRIN latch will be set on the rising

edge of the PWRIN signal. Undefined after reset.

RESHSYLAT. Resets the HSYNC latch; this bit is

set only.

HSYINTEN. This bit enables the HSYNCN signal

(#0) from the latch to the ST6369 core. Undefined

after reset.

HSYEDGE. The bit determines the edge which will

cause the HSYNC latch to be set. If this bit is high,

than the HSYNC latch will be set on the rising edge

of the HSYNC signal. Undefined after reset.

42/67

®

Share Link: