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FIGURE 9-6:
WATCHDOG TIMER BLOCK DIAGRAM
From Timer0 Clock Source
(Figure 6-5)
Watchdog
Time
0
M
1U
X
Postscaler
WDT Enable
Configuration
Bit
PSA
8-to-1 MUX
PS<2:0>
0
1
MUX
To Timer0 (Figure 6-4)
PSA
WDT Time-out
TABLE 9-4: SUMMARY OF REGISTERS ASSOCIATED WITH THE WATCHDOG TIMER
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
Power-On
Reset
Value on
All Other
Resets
N/A
OPTION GPWU GPPU T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
Legend: Shaded boxes = Not used by Watchdog Timer, – = unimplemented, read as ‘0’, u = unchanged.
2004-2014 Microchip Technology Inc.
DS40001239F-page 41