PIC10F220IP(2006) View Datasheet(PDF) - Microchip Technology
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PIC10F220IP Datasheet PDF : 78 Pages
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PIC10F220/222
7.9 A/D Acquisition Requirements
For the ADC to meet its specified accuracy, the charge
holding capacitor (CHOLD) must be allowed to fully
charge to the input channel voltage level. The Analog
Input model is shown in Figure 7-1. The source
impedance (RS) and the internal sampling switch (RSS)
impedance directly affect the time required to charge the
capacitor CHOLD. The sampling switch (RSS) impedance
varies over the device voltage (VDD), see Figure 7-1.
The maximum recommended impedance for analog
sources is 10 kΩ. As the source impedance is
decreased, the acquisition time may be decreased.
After the analog input channel is selected (or changed),
an A/D acquisition must be done before the conversion
can be started. To calculate the minimum acquisition
time, Equation 7-1 may be used. This equation
assumes that 1/2 LSb error is used (256 steps for the
ADC). The 1/2 LSb error is the maximum error allowed
for the ADC to meet its specified resolution.
EQUATION 7-1: ACQUISITION TIME EXAMPLE
Assumptions: Temperature = 50°C and external impedance of 10kΩ 5.0V VDD
TACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient
= TAMP + TC + TCOFF
= 2µs + TC + [(Temperature - 25°C)(0.05µs/°C)]
Solving for TC:
TC = –CHOLD(RIC + RSS + RS) ln(1/512)
= –25pF(1kΩ + 7kΩ + 10kΩ) ln(0.00196)
= 2.81µs
Therefore:
TACQ = 2µS + 2.81µS + [(50°C- 25°C)(0.05µS/°C)]
= 6.06us
Note 1: The charge holding capacitor (CHOLD) is not discharged after each conversion.
2: The maximum recommended impedance for analog sources is 10 kΩ. This is required to meet the pin
leakage specification.
FIGURE 7-1:
ANALOG INPUT MODEL
Rs ANx
VDD
VT = 0.6V
RIC ≤ 1k
Sampling
Switch
SS Rss
VA
CPIN
5 pF
VT = 0.6V
I LEAKAGE
± 500 nA
CHOLD = 25 pF
VSS/VREF-
Legend: CPIN
= Input Capacitance
VT
= Threshold Voltage
I LEAKAGE = Leakage current at the pin due to
various junctions
RIC
= Interconnect Resistance
SS
= Sampling Switch
CHOLD = Sample/Hold Capacitance
6V
5V
RSS
VDD 4V
3V
2V
5 6 7 8 9 10 11
Sampling Switch
(kΩ)
DS41270B-page 32
Preliminary
© 2006 Microchip Technology Inc.
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