PIC12F629/675
TABLE 2-1: SPECIAL FUNCTION REGISTERS SUMMARY (CONTINUED)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOD
Page
Bank 1
80h
INDF(1)
Addressing this Location uses Contents of FSR to Address Data Memory
0000 0000
81h
OPTION_REG GPPU INTEDG T0CS
T0SE
PSA
PS2
PS1
PS0 1111 1111
82h
PCL
Program Counter's (PC) Least Significant Byte
0000 0000
83h
STATUS
IRP(2)
RP1(2)
RP0
TO
PD
Z
DC
C
0001 1xxx
84h
FSR
Indirect Data Memory Address Pointer
xxxx xxxx
85h
TRISIO
—
—
TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111
86h
—
Unimplemented
—
87h
—
Unimplemented
—
88h
—
Unimplemented
—
89h
—
Unimplemented
—
8Ah
PCLATH
—
—
—
Write Buffer for Upper 5 bits of Program Counter
---0 0000
8Bh
INTCON
GIE
PEIE
T0IE
INTE
GPIE
T0IF
INTF
GPIF 0000 0000
8Ch
PIE1
EEIE
ADIE
—
—
CMIE
—
—
TMR1IE 00-- 0--0
8Dh
—
Unimplemented
—
8Eh
PCON
—
—
—
—
—
—
POR
BOD ---- --0x
8Fh
—
Unimplemented
—
90h
OSCCAL
CAL5
CAL4
CAL3
CAL2
CAL1
CAL0
—
—
1000 00--
91h
—
Unimplemented
—
92h
—
Unimplemented
—
93h
—
Unimplemented
—
94h
—
Unimplemented
—
95h
WPU
—
—
WPU5
WPU4
—
WPU2
WPU1
WPU0 --11 -111
96h
IOC
—
—
IOC5
IOC4
IOC3
IOC2
IOC1
IOC0 --00 0000
97h
—
Unimplemented
—
98h
—
Unimplemented
—
99h
VRCON
VREN
—
VRR
—
VR3
VR2
VR1
VR0 0-0- 0000
9Ah
EEDATA
Data EEPROM Data Register
0000 0000
9Bh
EEADR
—
Data EEPROM Address Register
-000 0000
9Ch
EECON1
—
—
—
—
WRERR WREN
WR
RD
---- x000
9Dh
EECON2(1)
EEPROM Control Register 2
---- ----
9Eh
ADRESL(3)
Least Significant 2 bits of the Left Shifted A/D Result of 8 bits or the Right Shifted Result
xxxx xxxx
9Fh
ANSEL(3)
—
ADCS2 ADCS1 ADCS0
ANS3
ANS2
ANS1
ANS0 -000 1111
Legend:
Note 1:
2:
3:
— = unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition,
shaded = unimplemented
This is not a physical register.
These bits are reserved and should always be maintained as ‘0’.
PIC12F675 only.
18,59
12,28
17
11
18
19
—
—
—
—
17
13
14
—
16
—
16
—
—
—
—
20
21
—
—
40
47
47
48
48
42
44,59
DS41190C-page 10
2003 Microchip Technology Inc.