PIC12F629-I View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC12F629-I

8-Pin FLASH-Based 8-Bit CMOS Microcontrollers

Microchip Technology 

PIC12F629/675

REGISTER 6-2:

VRCON — VOLTAGE REFERENCE CONTROL REGISTER (ADDRESS: 99h)

R/W-0

U-0

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

VREN

—

VRR

—

VR3

VR2

VR1

VR0

bit 7

bit 0

bit 7

bit 6

bit 5

bit 4

bit 3-0

VREN: CVREF Enable bit

1 = CVREF circuit powered on

0 = CVREF circuit powered down, no IDD drain

Unimplemented: Read as '0'

VRR: CVREF Range Selection bit

1 = Low range

0 = High range

Unimplemented: Read as '0'

VR3:VR0: CVREF value selection 0 ≤ VR [3:0] ≤ 15

When VRR = 1: CVREF = (VR3:VR0 / 24) * VDD

When VRR = 0: CVREF = VDD/4 + (VR3:VR0 / 32) * VDD

Legend:

R = Readable bit

- n = Value at POR

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

6.9 Comparator Interrupts

The comparator interrupt flag is set whenever there is

a change in the output value of the comparator.

Software will need to maintain information about the

status of the output bits, as read from CMCON<6>, to

determine the actual change that has occurred. The

CMIF bit, PIR1<3>, is the comparator interrupt flag.

This bit must be reset in software by clearing it to ‘0’.

Since it is also possible to write a '1' to this register, a

simulated interrupt may be initiated.

The CMIE bit (PIE1<3>) and the PEIE bit

(INTCON<6>) must be set to enable the interrupt. In

addition, the GIE bit must also be set. If any of these

bits are cleared, the interrupt is not enabled, though the

CMIF bit will still be set if an interrupt condition occurs.

The user, in the Interrupt Service Routine, can clear the

interrupt in the following manner:

a) Any read or write of CMCON. This will end the

mismatch condition.

b) Clear flag bit CMIF.

A mismatch condition will continue to set flag bit CMIF.

Reading CMCON will end the mismatch condition, and

allow flag bit CMIF to be cleared.

Note:

If a change in the CMCON register (COUT)

should occur when a read operation is

being executed (start of the Q2 cycle), then

the CMIF (PIR1<3>) interrupt flag may not

get set.

TABLE 6-2: REGISTERS ASSOCIATED WITH COMPARATOR MODULE

Address Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

POR, BOD

Value on

all other

RESETS

0Bh/8Bh

0Ch

19h

8Ch

85h

99h

Legend:

INTCON GIE

PEIE T0IE INTE GPIE T0IF

INTF GPIF 0000 0000 0000 000u

PIR1

EEIF ADIF

—

—

CMIF

—

— TMR1IF 00-- 0--0 00-- 0--0

CMCON

—

COUT

—

CINV

CIS

CM2

CM1

CM0 -0-0 0000 -0-0 0000

PIE1

EEIE ADIE

—

—

CMIE

—

— TMR1IE 00-- 0--0 00-- 0--0

TRISIO

—

— TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111 --11 1111

VRCON VREN

—

VRR

—

VR3

VR2

VR1

VR0 0-0- 0000 0-0- 0000

x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by the comparator module.

DS41190C-page 40

 2003 Microchip Technology Inc.

Share Link: