PIC12F609/615/617/12HV609/615
12.6.2 WDT PROGRAMMING
CONSIDERATIONS
It should also be taken in account that under worst-
case conditions (i.e., VDD = Min., Temperature = Max.,
Max. WDT prescaler) it may take several seconds
before a WDT time out occurs.
FIGURE 12-2:
CLKOUT
(= FOSC/4)
WATCHDOG TIMER BLOCK DIAGRAM
0
T0CKI
pin
T0SE
1
0
T0CS
1
PSA
Watchdog
Timer
8-bit
Prescaler
8
3
PS<2:0>
1
SYNC 2
Cycles
0
PSA
1
WDT
Time-Out
0
WDTE
Note 1: T0SE, T0CS, PSA, PS<2:0> are bits in the OPTION register.
PSA
Data Bus
8
TMR0
Set Flag bit T0IF
on Overflow
TABLE 12-8: WDT STATUS
Conditions
WDTE = 0
CLRWDT Command
Oscillator Fail Detected
Exit Sleep + System Clock = T1OSC, EXTRC, INTRC, EXTCLK
Exit Sleep + System Clock = XT, HS, LP
WDT
Cleared
Cleared until the end of OST
TABLE 12-9: SUMMARY OF REGISTERS ASSOCIATED WITH WATCHDOG TIMER
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
OPTION_REG GPPU INTEDG T0CS T0SE PSA
PS2
PS1
CONFIG
IOSCFS CP MCLRE PWRTE WDTE FOSC2 FOSC1
Legend: Shaded cells are not used by the Watchdog Timer.
Note 1: See Register 12-1 for operation of all Configuration Word register bits.
PS0
FOSC0
1111 1111
—
1111 1111
—
DS41302D-page 122
2010 Microchip Technology Inc.