PIC12F617T-I/MS View Datasheet(PDF) - Microchip Technology
Part Name
Description
Manufacturer
PIC12F617T-I/MS Datasheet PDF : 212 Pages
| |||
PIC12F609/615/617/12HV609/615
TABLE 2-2: PIC12F615/617/HV615 SPECIAL FUNCTION REGISTERS SUMMARY BANK 0
Addr
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Page
Bank 0
00h INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
xxxx xxxx 25, 116
01h TMR0
Timer0 Module’s Register
xxxx xxxx 53, 116
02h PCL
Program Counter’s (PC) Least Significant Byte
0000 0000 25, 116
03h STATUS
IRP(1)
RP1(1)
RP0
TO
PD
Z
DC
C
0001 1xxx 18, 116
04h FSR
Indirect Data Memory Address Pointer
xxxx xxxx 25, 116
05h GPIO
—
—
GP5
GP4
GP3
GP2
GP1
GP0 --x0 x000 43, 116
06h
—
Unimplemented
—
—
07h
—
Unimplemented
—
—
08h
—
Unimplemented
—
—
09h
—
Unimplemented
—
—
0Ah PCLATH
—
—
—
Write Buffer for upper 5 bits of Program Counter
---0 0000 25, 116
0Bh INTCON
GIE
PEIE
T0IE
INTE
GPIE
T0IF
INTF
GPIF 0000 0000 20, 116
0Ch PIR1
—
ADIF
CCP1IF
—
CMIF
—
TMR2IF TMR1IF -00- 0-00 22, 116
0Dh
—
Unimplemented
—
—
0Eh TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
xxxx xxxx 57, 116
0Fh TMR1H
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
xxxx xxxx 57, 116
10h T1CON
T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 62, 116
11h
TMR2(3)
Timer2 Module Register
0000 0000 65, 116
12h T2CON(3)
—
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 66, 116
13h CCPR1L(3) Capture/Compare/PWM Register 1 Low Byte
XXXX XXXX 90, 116
14h CCPR1H(3) Capture/Compare/PWM Register 1 High Byte
XXXX XXXX 90, 116
15h CCP1CON(3)
P1M
—
DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0-00 0000 89, 116
16h PWM1CON(3) PRSEN
PDC6
PDC5
PDC4
PDC3
PDC2
PDC1
PDC0 0000 0000 105,
116
17h ECCPAS(3) ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0 0000 0000 102,
116
18h
—
Unimplemented
—
—
19h VRCON
CMVREN
—
VRR
FVREN
VR3
VR2
VR1
VR0 0-00 0000 76, 116
1Ah CMCON0
CMON
COUT
CMOE CMPOL
—
CMR
—
CMCH 0000 -0-0 72, 116
1Bh
—
—
—
—
—
1Ch CMCON1
—
—
—
T1ACS CMHYS
—
T1GSS CMSYNC ---0 0-10 73, 116
1Dh
—
Unimplemented
—
—
1Eh ADRESH(2, 3) Most Significant 8 bits of the left shifted A/D result or 2 bits of right shifted result
xxxx xxxx 85, 116
1Fh ADCON0(3)
ADFM
VCFG
—
CHS2
CHS1
CHS0 GO/DONE ADON 00-0 0000 84, 116
Legend:
Note 1:
2:
3:
– = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
IRP and RP1 bits are reserved, always maintain these bits clear.
Read only register.
PIC12F615/617/HV615 only.
2010 Microchip Technology Inc.
DS41302D-page 15
Share Link: 