PIC16C65B-04E/SP View Datasheet(PDF) - Microchip Technology
Part Name
Description
Manufacturer
PIC16C65B-04E/SP Datasheet PDF : 184 Pages
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PIC16C63A/65B/73B/74B
FIGURE 16-15:
SS
EXAMPLE SPI SLAVE MODE TIMING (CKE = 1)
82
70
SCK
(CKP = 0)
83
71
72
SCK
(CKP = 1)
80
SDO
MSb
BIT6 - - - - - -1
LSb
75, 76
77
SDI
MSb IN
BIT6 - - - -1
LSb IN
74
Note: Refer to Figure 16-4 for load conditions.
TABLE 16-11: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1)
Param
No.
Symbol
Characteristic
Min
Typ† Max Units
Conditions
70 TssL2scH, SS↓ to SCK↓ or SCK↑ input
TssL2scL
71 TscH
71A
SCK input high time
(Slave mode)
Continuous
Single Byte
72 TscL
72A
SCK input low time
(Slave mode)
Continuous
Single Byte
TCY
— — ns
1.25TCY + 30 — — ns
40
— — ns (Note 1)
1.25TCY + 30 — — ns
40
— — ns (Note 1)
73A TB2B
Last clock edge of Byte1 to the 1st clock 1.5TCY + 40
edge of Byte2
74
TscH2diL,
TscL2diL Hold time of SDI data input to SCK edge
100
75 TdoR
SDO data output rise
time
PIC16CXX
PIC16LCXX
—
76 TdoF
SDO data output fall time
—
77 TssH2doZ SS↑ to SDO output hi-impedance
10
78 TscR
SCK output rise time PIC16CXX
—
(Master mode)
PIC16LCXX
—
79 TscF
SCK output fall time (Master mode)
—
80
TscH2doV, SDO data output valid PIC16CXX
TscL2doV after SCK edge
PIC16LCXX
—
—
82 TssL2doV SDO data output valid PIC16CXX
—
after SS↓ edge
PIC16LCXX
—
83
TscH2ssH,
TscL2ssH SS ↑ after SCK edge
1.5TCY + 40
— — ns (Note 1)
— — ns
10 25 ns
20 45 ns
10 25 ns
— 50 ns
10 25 ns
20 45 ns
10 25 ns
— 50 ns
— 100 ns
— 50 ns
— 100 ns
— — ns
† Data in “Typ” column is at 5 V, 25°C unless otherwise stated. These parameters are for design guidance only and
are not tested.
Note 1: Specification 73A is only required if specifications 71A and 72A are used.
2000 Microchip Technology Inc.
DS30605C-page 133
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