PIC16LC62T-10E/SP View Datasheet(PDF) - Microchip Technology
Part Name
Description
Manufacturer
PIC16LC62T-10E/SP Datasheet PDF : 336 Pages
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Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
PIC16C6X
11.5.1.2 RECEPTION
When the R/W bit of the address byte is clear and an
address match occurs, the R/W bit of the SSPSTAT reg-
ister is cleared. The received address is loaded into the
SSPBUF register.
When the address byte overflow condition exists, then
no acknowledge (ACK) pulse is given. An overflow con-
dition is defined as either bit BF (SSPSTAT<0>) is set
or bit SSPOV (SSPCON<6>) is set.
An SSP interrupt is generated for each data transfer
byte. Flag bit SSPIF (PIR1<3>) must be cleared in soft-
ware. The SSPSTAT register is used to determine the
status of the byte.
FIGURE 11-25: I2C WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)
SDA
Receiving Address R/W=0
Receiving Data
ACK
Receiving Data
ACK
A7 A6 A5 A4 A3 A2 A1
ACK D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
SCL S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
P
SSPIF (PIR1<3>)
BF (SSPSTAT<0>)
Cleared in software
SSPBUF register is read
Bus Master
terminates
transfer
SSPOV (SSPCON<6>)
Bit SSPOV is set because the SSPBUF register is still full.
ACK is not sent.
© 1997 Microchip Technology Inc.
DS30234D-page 101
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