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PIC16LCR64A-04E/SO View Datasheet(PDF) - Microchip Technology

Part Name
Description
Manufacturer
PIC16LCR64A-04E/SO
Microchip
Microchip Technology 
PIC16LCR64A-04E/SO Datasheet PDF : 336 Pages
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PIC16C6X
NOP
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
No Operation
[ label ] NOP
None
No operation
None
00 0000 0xx0 0000
No operation.
1
1
Q1
Q2
Q3
Q4
Decode
No-
No-
No-
Operation Operation Operation
Example
NOP
OPTION
Load Option Register
Syntax:
[ label ] OPTION
Operands:
None
Operation:
(W) OPTION
Status Affected: None
Encoding:
00 0000 0110 0010
Description:
The contents of the W register are
loaded in the OPTION register. This
instruction is supported for code com-
patibility with PIC16C5X products.
Since OPTION is a readable/writable
register, the user can directly address
it.
Words:
1
Cycles:
1
Example
To maintain upward compatibility
with future PIC16CXX products, do
not use this instruction.
RETFIE
Return from Interrupt
Syntax:
[ label ] RETFIE
Operands:
None
Operation:
TOS PC,
1 GIE
Status Affected: None
Encoding:
00 0000 0000 1001
Description:
Return from Interrupt. Stack is POPed
and Top of Stack (TOS) is loaded in the
PC. Interrupts are enabled by setting
Global Interrupt Enable bit, GIE
(INTCON<7>). This is a two cycle
instruction.
Words:
1
Cycles:
2
Q Cycle Activity:
Q1
Q2
Q3
Q4
1st Cycle Decode
No-
Set the Pop from
Operation GIE bit the Stack
2nd Cycle No-
No-
No-
No-
Operation Operation Operation Operation
Example
RETFIE
After Interrupt
PC = TOS
GIE = 1
© 1997 Microchip Technology Inc.
DS30234D-page 153

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