PIC16LC64-10I/P View Datasheet(PDF) - Microchip Technology
Part Name
Description
Manufacturer
PIC16LC64-10I/P Datasheet PDF : 336 Pages
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PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
FIGURE 18-10: I2C BUS DATA TIMING
SCL
SDA
In
103
90
91
109
100
101
106 107
109
102
92
110
SDA
Out
Note: Refer to Figure 18-1 for load conditions
TABLE 18-10: I2C BUS DATA REQUIREMENTS
Parameter
No.
Sym
Characteristic
Min
Max Units
Conditions
100
101
102
103
90
91
106
107
92
109
110
Note 1:
2:
THIGH Clock high time
100 kHz mode
4.0
—
µs Device must operate at a min-
imum of 1.5 MHz
400 kHz mode
0.6
—
µs Device must operate at a min-
imum of 10 MHz
SSP Module
1.5TCY
—
TLOW Clock low time
100 kHz mode
4.7
—
µs Device must operate at a min-
imum of 1.5 MHz
400 kHz mode
1.3
—
µs Device must operate at a min-
imum of 10 MHz
SSP Module
1.5TCY
—
TR SDA and SCL rise
time
100 kHz mode
400 kHz mode
—
1000
20 + 0.1Cb 300
ns
ns Cb is specified to be from
10 to 400 pF
TF SDA and SCL fall time 100 kHz mode
—
300
ns
400 kHz mode 20 + 0.1Cb 300
ns Cb is specified to be from
10 to 400 pF
TSU:STA START condition
setup time
100 kHz mode
400 kHz mode
4.7
—
µs Only relevant for repeated
0.6
—
µs START condition
THD:STA START condition hold 100 kHz mode
time
400 kHz mode
4.0
—
µs After this period the first clock
0.6
—
µs pulse is generated
THD:DAT Data input hold time 100 kHz mode
0
—
ns
400 kHz mode
0
0.9
µs
TSU:DAT Data input setup time 100 kHz mode
250
—
ns Note 2
400 kHz mode
100
—
ns
TSU:STO STOP condition setup 100 kHz mode
time
400 kHz mode
4.7
—
µs
0.6
—
µs
TAA Output valid from
clock
100 kHz mode
400 kHz mode
—
3500 ns Note 1
—
—
ns
TBUF Bus free time
100 kHz mode
400 kHz mode
4.7
—
µs Time the bus must be free
1.3
—
µs before a new transmission can
start
Cb Bus capacitive loading
—
400 pF
As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of
the falling edge of SCL to avoid unintended generation of START or STOP conditions.
A fast-mode (400 kHz) I2C-bus device can be used in a standard-mode (100 kHz) I2C-bus system, but the requirement
tsu;DAT ≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the
SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line
TR max. + tsu;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I2C bus specification) before the SCL line is
released.
© 1997 Microchip Technology Inc.
DS30234D-page 197
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