PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
FIGURE 19-9: SPI MODE TIMING
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
70
71
72
78
79
80
79
78
SDO
75, 76
77
SDI
74
73
Note: Refer to Figure 19-1 for load conditions
TABLE 19-8: SPI MODE REQUIREMENTS
Parameter
No.
Sym
Characteristic
Min
Typ† Max Units Conditions
70*
TssL2scH, SS↓ to SCK↓ or SCK↑ input
TssL2scL
TCY
—
—
ns
71*
TscH
SCK input high time (slave mode) TCY + 20
—
—
ns
72*
TscL
SCK input low time (slave mode)
TCY + 20
—
—
ns
73*
TdiV2scH, Setup time of SDI data input to SCK
50
TdiV2scL
edge
—
—
ns
74*
TscH2diL, Hold time of SDI data input to SCK
50
TscL2diL
edge
—
—
ns
75*
TdoR
SDO data output rise time
—
10
25
ns
76*
TdoF
SDO data output fall time
—
10
25
ns
77*
TssH2doZ SS↑ to SDO output hi-impedance
10
—
50
ns
78*
TscR
SCK output rise time (master mode)
—
10
25
ns
79*
TscF
SCK output fall time (master mode)
—
10
25
ns
80*
TscH2doV, SDO data output valid after SCK
—
—
50
ns
TscL2doV edge
* These parameters are characterized but not tested.
† Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
© 1997 Microchip Technology Inc.
DS30234D-page 211