PIC16C6X
FIGURE 4-8: PIC16C66/67 DATA MEMORY MAP
Indirect addr.(*) 00h
TMR0
01h
PCL
02h
STATUS 03h
FSR
04h
PORTA
05h
PORTB 06h
PORTC 07h
PORTD (1) 08h
PORTE (1) 09h
PCLATH 0Ah
INTCON 0Bh
PIR1
0Ch
PIR2
0Dh
TMR1L
0Eh
TMR1H 0Fh
T1CON 10h
TMR2
11h
T2CON 12h
SSPBUF 13h
SSPCON 14h
CCPR1L 15h
CCPR1H 16h
CCP1CON 17h
RCSTA
18h
TXREG 19h
RCREG 1Ah
CCPR2L 1Bh
CCPR2H 1Ch
CCP2CON 1Dh
1Eh
1Fh
20h
Indirect addr.(*) 80h
OPTION 81h
PCL
82h
STATUS 83h
FSR
84h
TRISA
85h
TRISB
86h
TRISC
87h
TRISD (1) 88h
TRISE (1) 89h
PCLATH 8Ah
INTCON 8Bh
PIE1
8Ch
PIE2
8Dh
PCON
8Eh
8Fh
90h
91h
PR2
92h
SSPADD 93h
SSPSTAT 94h
95h
96h
97h
TXSTA
98h
SPBRG
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
A0h
Indirect addr.(*)
TMR0
PCL
STATUS
FSR
PORTB
PCLATH
INTCON
General
Purpose
Register
16 Bytes
100h
101h
102h
103h
104h
105h
106h
107h
108h
109h
10Ah
10Bh
10Ch
10Dh
10Eh
10Fh
110h
111h
112h
113h
114h
115h
116h
117h
118h
119h
11Ah
11Bh
11Ch
11Dh
11Eh
11Fh
120h
File
Address
Indirect addr.(*)
OPTION
PCL
STATUS
FSR
TRISB
PCLATH
INTCON
General
Purpose
Register
16 Bytes
180h
181h
182h
183h
184h
185h
186h
187h
188h
189h
18Ah
18Bh
18Ch
18Dh
18Eh
18Fh
190h
191h
192h
193h
194h
195h
196h
197h
198h
199h
19Ah
19Bh
19Ch
19Dh
19Eh
19Fh
1A0h
General
Purpose
Register
96 Bytes
7Fh
Bank 0
General
Purpose
Register
80 Bytes
EFh
accesses F0h
70h-7Fh
in Bank 0
FFh
Bank 1
General
Purpose
Register
80 Bytes
accesses
70h-7Fh
in Bank 0
Bank 2
16Fh
170h
17Fh
General
Purpose
Register
80 Bytes
accesses
70h-7Fh
in Bank 0
Bank 3
1EFh
1F0h
1FFh
Unimplemented data memory locations, read as '0'.
* Not a physical register.
These registers are not implemented on the PIC16C66.
Note: The upper 16 bytes of data memory in banks 1, 2, and 3 are mapped in Bank 0. This may require
relocation of data memory usage in the user application code if upgrading to the PIC16C66/67.
DS30234D-page 22
© 1997 Microchip Technology Inc.