PIC16CR63-20I View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC16CR63-20I

8-Bit CMOS Microcontrollers

Microchip Technology 

PIC16C6X

TABLE 4-6: SPECIAL FUNCTION REGISTERS FOR THE PIC16C66/67 (Cont.’d)

Address Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on:

POR,

BOR

Value on

all other

resets(3)

Bank 2

100h(1) INDF

101h TMR0

102h(1) PCL

103h(1) STATUS

104h(1) FSR

105h

—

106h PORTB

107h

—

108h

—

109h

—

10Ah(1,2) PCLATH

10Bh(1) INTCON

10Ch-

10Fh

—

Addressing this location uses contents of FSR to address data memory (not a physical register)

Timer0 module’s register

Program Counter's (PC) Least Significant Byte

IRP

RP1

RP0

TO

PD

Z

DC

C

Indirect data memory address pointer

Unimplemented

PORTB Data Latch when written: PORTB pins when read

Unimplemented

Unimplemented

Unimplemented

—

—

— Write Buffer for the upper 5 bits of the Program Counter

GIE

PEIE

T0IE

INTE

RBIE

T0IF

INTF

RBIF

Unimplemented

0000 0000 0000 0000

xxxx xxxx uuuu uuuu

0000 0000 0000 0000

0001 1xxx 000q quuu

xxxx xxxx uuuu uuuu

—

—

xxxx xxxx uuuu uuuu

—

—

—

—

—

—

---0 0000 ---0 0000

0000 000x 0000 000u

—

—

Bank 3

180h(1) INDF

Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000

181h OPTION

RBPU INTEDG T0CS

T0SE

PSA

PS2

PS1

PS0 1111 1111 1111 1111

182h(1) PCL

Program Counter's (PC) Least Significant Byte

0000 0000 0000 0000

183h(1) STATUS

IRP

RP1

RP0

TO

PD

Z

DC

C

0001 1xxx 000q quuu

184h(1) FSR

Indirect data memory address pointer

xxxx xxxx uuuu uuuu

185h

—

Unimplemented

—

—

186h

TRISB

PORTB Data Direction Register

1111 1111 1111 1111

187h

—

Unimplemented

—

—

188h

—

Unimplemented

—

—

189h

—

Unimplemented

—

—

18Ah(1,2) PCLATH

—

—

— Write Buffer for the upper 5 bits of the Program Counter

---0 0000 ---0 0000

18Bh(1) INTCON

GIE

PEIE

T0IE

INTE

RBIE

T0IF

INTF

RBIF 0000 000x 0000 000u

18Ch-

19Fh

—

Unimplemented

—

—

Legend:

Note 1:

2:

3:

4:

5:

6:

x = unknown, u = unchanged, q = value depends on condition, - = unimplemented location read as '0'.

Shaded locations are unimplemented, read as ‘0’.

These registers can be addressed from any bank.

The upper byte of the Program Counter (PC) is not directly accessible. PCLATH is a holding register for the PC whose

contents are transferred to the upper byte of the program counter. (PC<12:8>)

Other (non power-up) resets include external reset through MCLR and the Watchdog Timer reset.

PIE1<6> and PIR1<6> are reserved on the PIC16C66/67, always maintain these bits clear.

PORTD, PORTE, TRISD, and TRISE are not implemented on the PIC16C66, read as '0'.

PSPIF (PIR1<7>) and PSPIE (PIE1<7>) are reserved on the PIC16C66, maintain these bits clear.

DS30234D-page 34

© 1997 Microchip Technology Inc.

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