PIC16CR65AT-10/SS View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC16CR65AT-10/SS

8-Bit CMOS Microcontrollers

Microchip Technology 

5.0 I/O PORTS

Applicable Devices

61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

Some pins for these I/O ports are multiplexed with an

alternate function(s) for the peripheral features on the

device. In general, when a peripheral is enabled, that

pin may not be used as a general purpose I/O pin.

5.1 PORTA and TRISA Register

Applicable Devices

61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

All devices have a 6-bit wide PORTA, except for the

PIC16C61 which has a 5-bit wide PORTA.

Pin RA4/T0CKI is a Schmitt Trigger input and an open

drain output. All other RA port pins have TTL input lev-

els and full CMOS output drivers. All pins have data

direction bits (TRIS registers) which can configure

these pins as output or input.

Setting a bit in the TRISA register puts the correspond-

ing output driver in a hi-impedance mode. Clearing a bit

in the TRISA register puts the contents of the output

latch on the selected pin.

Reading PORTA register reads the status of the pins

whereas writing to it will write to the port latch. All write

operations are read-modify-write operations. There-

fore, a write to a port implies that the port pins are read,

this value is modified, and then written to the port data

latch.

Pin RA4 is multiplexed with Timer0 module clock input

to become the RA4/T0CKI pin.

EXAMPLE 5-1: INITIALIZING PORTA

BCF

BCF

CLRF

BSF

MOVLW

MOVWF

STATUS, RP0

STATUS, RP1

PORTA

STATUS, RP0

0xCF

TRISA

;

; PIC16C66/67 only

; Initialize PORTA by

; clearing output

; data latches

; Select Bank 1

; Value used to

; initialize data

; direction

; Set RA<3:0> as inputs

; RA<5:4> as outputs

; TRISA<7:6> are always

; read as '0'.

PIC16C6X

FIGURE 5-1:

BLOCK DIAGRAM OF THE

RA3:RA0 PINS AND THE RA5

PIN

Data

bus

WR

Port

D

Q

CK Q

Data Latch

D

Q

VDD

P

N

I/O pin(1)

WR

TRIS

CK Q

TRIS Latch

VSS

TTL

input

buffer

RD TRIS

Q

D

EN

RD PORT

Note 1: I/O pins have protection diodes to VDD and

VSS.

2: The PIC16C61 does not have an RA5 pin.

FIGURE 5-2: BLOCK DIAGRAM OF THE

RA4/T0CKI PIN

Data

bus

WR

PORT

DQ

CK Q

Data Latch

N

I/O pin(1)

WR

TRIS

DQ

CK Q

TRIS Latch

VSS

Schmitt

Trigger

input

buffer

RD TRIS

Q

D

RD PORT

ENEN

TMR0 clock input

Note 1: I/O pin has protection diodes to VSS only.

© 1997 Microchip Technology Inc.

DS30234D-page 51

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