PIC16C62B/72A
FIGURE 13-17: A/D CONVERSION TIMING
BSF ADCON0, GO
1 TCY
134
(Tosc/2) (1)
131
Q4
130
A/D CLK 132
A/D DATA
7
6
5
4
3
2
1
0
ADRES
OLD_DATA
NEW_DATA
ADIF
GO
SAMPLE
SAMPLING STOPPED
DONE
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This
allows the SLEEP instruction to be executed.
TABLE 13-14: A/D CONVERSION REQUIREMENTS
Param Sym Characteristic
Min
No.
130 TAD A/D clock period
PIC16CXX
1.6
PIC16LCXX
2.0
PIC16CXX
2.0
PIC16LCXX
3.0
131 TCNV Conversion time (not including S/H 11
time) (Note 1)
132 TACQ Acquisition time
Note 2
Typ†
—
—
4.0
6.0
—
20
Max
—
—
6.0
9.0
11
Unit
Conditions
s
µs TOSC based, VREF ≥ 3.0V
µs TOSC based, VREF full range
µs A/D RC Mode
µs A/D RC Mode
TAD
— µs
5*
—
— µs The minimum time is the
amplifier settling time. This
may be used if the "new" input
voltage has not changed by
more than 1 LSb (i.e., 20.0 mV
@ 5.12V) from the last sam-
pled voltage (as stated on
CHOLD).
134 TGO
Q4 to A/D clock start
— TOSC/2 —
— If the A/D clock source is
selected as RC, a time of TCY
is added before the A/D clock
starts. This allows the SLEEP
instruction to be executed.
135 Tswc Switching from convert → sample
1.5
—
time
— TAD
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: ADRES register may be read on the following TCY cycle.
2: See Section 9.1 for min conditions.
DS35008B-page 102
Preliminary
© 1998 Microchip Technology Inc.