PIC16LC62B-04I/SO View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC16LC62B-04I/SO

28-Pin 8-Bit CMOS Microcontrollers

Microchip Technology 

PIC16C62B/72A

7.2 Compare Mode

In Compare mode, the 16-bit CCPR1 register value is

constantly compared against the TMR1 register pair

value. When a match occurs, the RC2/CCP1 pin is:

• driven High

• driven Low

• remains Unchanged

The action on the pin is based on the value of control

bits CCP1M3:CCP1M0 (CCP1CON<3:0>). The inter-

rupt flag bit, CCP1IF, is set on all compare matches.

FIGURE 7-2:

COMPARE MODE

OPERATION BLOCK

DIAGRAM

Special event trigger will:

reset Timer1, but not set interrupt flag bit TMR1IF (PIR1<0>),

and set bit GO/DONE (ADCON0<2>), which starts an A/D

conversion

Special Event Trigger

Set flag bit CCP1IF

(PIR1<2>)

CCPR1H CCPR1L

Q

RC2/CCP1

Pin

TRISC<2>

Output Enable

S Output

R Logic

match

CCP1CON<3:0>

Mode Select

Comparator

TMR1H TMR1L

7.2.1 CCP PIN CONFIGURATION

The user must configure the RC2/CCP1 pin as an out-

put by clearing the TRISC<2> bit.

Note:

Clearing the CCP1CON register will force

the RC2/CCP1 compare output latch to the

default low level. This is not the data latch.

7.2.2 TIMER1 MODE SELECTION

Timer1 must be running in Timer mode or Synchro-

nized Counter mode if the CCP module is using the

compare feature. In Asynchronous Counter mode, the

compare operation may not work.

7.2.3 SOFTWARE INTERRUPT MODE

When a generated software interrupt is chosen, the

CCP1 pin is not affected. Only a CCP interrupt is gen-

erated (if enabled).

7.2.4 SPECIAL EVENT TRIGGER

In this mode, an internal hardware trigger is generated,

which may be used to initiate an action.

The special event trigger output of CCP1 resets the

TMR1 register pair. This allows the CCPR1 register to

effectively be a 16-bit programmable period register for

Timer1.

The special trigger output of CCP1 resets the TMR1

register pair and starts an A/D conversion (if the A/D

module is enabled).

TABLE 7-3 REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, AND TIMER1

Address Name

Bit 7 Bit 6 Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

POR,

BOR

Value on

all other

resets

0Bh,8Bh INTCON

GIE PEIE T0IE

INTE

RBIE

T0IF INTF RBIF 0000 000x 0000 000u

0Ch

PIR1

— ADIF —

—

SSPIF CCP1IF TMR2IF TMR1IF -0-- 0000 -0-- 0000

8Ch

PIE1

— ADIE —

—

SSPIE CCP1IE TMR2IE TMR1IE -0-- 0000 -0-- 0000

87h

TRISC PORTC Data Direction Register

1111 1111 1111 1111

0Eh

TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register

xxxx xxxx uuuu uuuu

0Fh

TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1register

xxxx xxxx uuuu uuuu

10h

T1CON

—

— T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu

15h

CCPR1L Capture/Compare/PWM register1 (LSB)

xxxx xxxx uuuu uuuu

16h

CCPR1H Capture/Compare/PWM register1 (MSB)

xxxx xxxx uuuu uuuu

17h

CCP1CON —

— CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000

Legend: x = unknown, u = unchanged, - = unimplemented read as ’0’. Shaded cells are not used by Capture and Timer1.

© 1999 Microchip Technology Inc.

Preliminary

DS35008B-page 35

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