PIC16LC62B-04I/SO View Datasheet(PDF) - Microchip Technology
Part Name
Description
Manufacturer
PIC16LC62B-04I/SO Datasheet PDF : 120 Pages
| |||
PIC16C62B/72A
FIGURE 13-14: EXAMPLE SPI SLAVE MODE TIMING (CKE = 1)
82
SS
70
SCK
(CKP = 0)
83
71
72
SCK
(CKP = 1)
80
SDO
MSb
BIT6 - - - - - -1
LSb
75, 76
77
SDI
MSb IN
BIT6 - - - -1
LSb IN
74
NOTE: Refer to Figure 13-4 for load conditions.
TABLE 13-10: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1)
Param. Symbol
No.
70
TssL2scH,
TssL2scL
Characteristic
SS↓ to SCK↓ or SCK↑ input
Min
Typ† Max Units Conditions
TCY
— — ns
71
TscH
71A
72
TscL
72A
SCK input high time
(slave mode)
SCK input low time
(slave mode)
Continuous
Single Byte
Continuous
Single Byte
1.25TCY + 30 — — ns
40
— — ns Note 1
1.25TCY + 30 — — ns
40
— — ns Note 1
73A
TB2B
Last clock edge of Byte1 to the 1st clock 1.5TCY + 40 — — ns Note 1
edge of Byte2
74
TscH2diL, Hold time of SDI data input to SCK edge
100
TscL2diL
— — ns
75
TdoR
SDO data output rise
time
PIC16CXX
PIC16LCXX
—
10 25 ns
20 45 ns
76
TdoF
SDO data output fall time
77
TssH2doZ SS↑ to SDO output hi-impedance
78
TscR
SCK output rise time
(master mode)
PIC16CXX
PIC16LCXX
79
TscF
SCK output fall time (master mode)
—
10 25 ns
10
— 50 ns
—
10 25 ns
—
20 45 ns
—
10 25 ns
80
TscH2doV, SDO data output valid PIC16CXX
TscL2doV after SCK edge
PIC16LCXX
—
— 50 ns
—
— 100 ns
82
TssL2doV SDO data output valid PIC16CXX
after SS↓ edge
PIC16LCXX
—
— 50 ns
—
— 100 ns
83
TscH2ssH, SS ↑ after SCK edge
TscL2ssH
1.5TCY + 40 — — ns
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: Specification 73A is only required if specifications 71A and 72A are used.
DS35008B-page 98
Preliminary
© 1998 Microchip Technology Inc.
Share Link: 