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PIC16C774T-I/SO View Datasheet(PDF) - Microchip Technology

Part Name
Description
Manufacturer
PIC16C774T-I/SO
Microchip
Microchip Technology 
PIC16C774T-I/SO Datasheet PDF : 202 Pages
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PIC16C77X
TABLE 2-1 PIC16C77X SPECIAL FUNCTION REGISTER SUMMARY (Cont.’d)
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on: Value on all
POR, other resets
BOR
(2)
Bank 1
80h(4)
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000 0000 0000
81h
OPTION_REG RBPU INTEDG T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111 1111 1111
82h(4)
PCL
Program Counter's (PC) Least Significant Byte
0000 0000 0000 0000
83h(4)
STATUS
IRP
RP1
RP0
TO
PD
Z
DC
C
0001 1xxx 000q quuu
84h(4)
FSR
Indirect data memory address pointer
xxxx xxxx uuuu uuuu
85h
TRISA
bit5(5)
PORTA Data Direction Register
--11 1111 --11 1111
86h
TRISB
PORTB Data Direction Register
1111 1111 1111 1111
87h
88h(5)
89h(5)
8Ah(1,4)
8Bh(4)
8Ch
TRISC
TRISD
TRISE
PCLATH
INTCON
PIE1
PORTC Data Direction Register
PORTD Data Direction Register
IBF
OBF
IBOV
GIE
PSPIE(3)
PEIE
ADIE
T0IE
RCIE
PSPMODE
PORTE Data Direction Bits
Write Buffer for the upper 5 bits of the Program Counter
INTE
RBIE
T0IF
INTF
RBIF
TXIE
SSPIE CCP1IE TMR2IE TMR1IE
1111 1111
1111 1111
0000 -111
---0 0000
0000 000x
0000 0000
1111 1111
1111 1111
0000 -111
---0 0000
0000 000u
0000 0000
8Dh
PIE2
LVDIE
BCLIE
CCP2IE 0--- 0--0
0--- 0--0
8Eh
PCON
POR
BOR
---- --qq
---- --uu
8Fh
Unimplemented
90h
Unimplemented
91h
SSPCON2
GCEN AKSTAT
AKDT
AKEN
RCEN
PEN
RSEN
SEN
0000 0000 0000 0000
92h
PR2
Timer2 Period Register
93h
SSPADD Synchronous Serial Port (I2C mode) Address Register
1111 1111
0000 0000
1111 1111
0000 0000
94h
SSPSTAT
SMP
CKE
D/A
P
S
R/W
UA
BF
0000 0000 0000 0000
95h
Unimplemented
96h
Unimplemented
97h
Unimplemented
98h
TXSTA
CSRC
TX9
TXEN
SYNC
BRGH
TRMT
TX9D
0000 -010 0000 -010
99h
SPBRG
Baud Rate Generator Register
0000 0000 0000 0000
9Ah
Unimplemented
9Bh
REFCON
VRHEN VRLEN VRHOEN VRLOEN
0000 ----
0000 ----
9Ch
LVDCON
BGST
LVDEN
LV3
LV2
LV1
LV0
--00 0101 --00 0101
9Ah
Unimplemented
9Eh
ADRESL A/D Low Byte Result Register
xxxx xxxx uuuu uuuu
9Fh
ADCON1
ADFM VCFG2 VCFG1
VCFG0
PCFG3 PCFG2 PCFG1 PCFG0 0000 0000 0000 0000
Legend:
Note 1:
2:
3:
4:
5:
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'.
Shaded locations are unimplemented, read as ‘0’.
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents are transferred to
the upper byte of the program counter.
Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.
Bits PSPIE and PSPIF are reserved on the 28-pin devices, always maintain these bits clear.
These registers can be addressed from any bank.
These registers/bits are not implemented on the 28-pin devices read as '0'.
DS30275B-page 14
Advance Information
1999-2013 Microchip Technology Inc.

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