PIC16LC773-I/SS View Datasheet(PDF) - Microchip Technology
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PIC16LC773-I/SS Datasheet PDF : 202 Pages
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3.2 PORTB and the TRISB Register
PORTB is an 8-bit wide bi-directional port. The corre-
sponding data direction register is TRISB. Setting a
TRISB bit (=1) will make the corresponding PORTB pin
an input, i.e., put the corresponding output driver in a
hi-impedance mode. Clearing a TRISB bit (=0) will
make the corresponding PORTB pin an output, i.e., put
the contents of the output latch on the selected pin.
EXAMPLE 3-1: INITIALIZING PORTB
BCF STATUS, RP0 ;
CLRF PORTB
; Initialize PORTB by
; clearing output
; data latches
BSF STATUS, RP0 ; Select Bank 1
MOVLW 0xCF
; Value used to
; initialize data
; direction
MOVWF TRISB
; Set RB<3:0> as inputs
; RB<5:4> as outputs
; RB<7:6> as inputs
Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is per-
formed by clearing bit RBPU (OPTION_REG<7>). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are dis-
abled on a Power-on Reset.
The RB0 pin is multiplexed with the external interrupt
(RB0/INT).
FIGURE 3-4:
RBPU(2)
Data bus
WR Port
WR TRIS
BLOCK DIAGRAM OF RB0 PIN
VDD
Data Latch
DQ
P
weak
pull-up
I/O
CK
pin(1)
TRIS Latch
DQ
CK
TTL
Input
Buffer
RD TRIS
RD Port
QD
EN
RB0/INT
Schmitt Trigger
Buffer
RD Port
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS bit(s)
and clear the RBPU bit (OPTION_REG<7>).
PIC16C77X
The RB1 pin is multiplexed with the SSP module slave
select (RB1/SS).
FIGURE 3-5:
RBPU(2)
Data bus
WR Port
WR TRIS
BLOCK DIAGRAM OF RB1/SS
PIN
VDD
Data Latch
DQ
P
weak
pull-up
I/O
CK
pin(1)
TRIS Latch
DQ
CK
TTL
Input
Buffer
RD TRIS
RD Port
Q
D
EN
SS input
Schmitt Trigger
Buffer
RD Port
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS bit(s)
and clear the RBPU bit (OPTION_REG<7>).
The RB2 pin is multiplexed with analog channel 8
(RB2/AN8).
FIGURE 3-6: BLOCK DIAGRAM OF
RB2/AN8 PIN
RBPU(2)
VDD
P
weak
pull-up
Data bus
Data Latch
DQ
WR Port
CK
TRIS Latch
DQ
I/O
pin(1)
WR TRIS
CK
Analog
input mode
RD TRIS
TTL
Input
Buffer
QD
RD Port
EN
To A/D converter
RD Port
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS bit(s)
and clear the RBPU bit (OPTION_REG<7>).
1999-2013 Microchip Technology Inc.
Advance Information
DS30275B-page 29
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