PIC16LC773T-/PQ View Datasheet(PDF) - Microchip Technology
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Description
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PIC16LC773T-/PQ Datasheet PDF : 202 Pages
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PIC16C77X
4.2.1 SWITCHING PRESCALER ASSIGNMENT
The prescaler assignment is fully under software con-
trol, i.e., it can be changed “on the fly” during program
execution.
Note:
To avoid an unintended device RESET, a
specific instruction sequence (shown in the
PICmicro™ Mid-Range Reference Man-
ual, DS33023) must be executed when
changing the prescaler assignment from
Timer0 to the WDT. This sequence must
be followed even if the WDT is disabled.
4.3 Timer0 Interrupt
The TMR0 interrupt is generated when the TMR0 reg-
ister overflows from FFh to 00h. This overflow sets bit
T0IF (INTCON<2>). The interrupt can be masked by
clearing bit T0IE (INTCON<5>). Bit T0IF must be
cleared in software by the Timer0 module interrupt ser-
vice routine before re-enabling this interrupt. The
TMR0 interrupt cannot awaken the processor from
SLEEP since the timer is shut off during SLEEP.
FIGURE 4-2: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
CLKOUT (=Fosc/4)
Data Bus
RA4/T0CKI
pin
T0SE
0M
U
X
1
T0CS
1
M
0
U
X
PSA
SYNC
2
Cycles
8
TMR0 reg
Set flag bit T0IF
on Overflow
Watchdog
Timer
WDT Enable bit
0
M
U
1X
PSA
8-bit Prescaler
8
8 - to - 1MUX
PS2:PS0
0
1
MUX
PSA
WDT
Time-out
Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION_REG<5:0>).
TABLE 4-1 REGISTERS ASSOCIATED WITH TIMER0
Address Name
Bit 7
Bit 6
Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
Bit 0
Value on:
POR,
BOR
Value on all
other resets
01h,101h TMR0
Timer0 module’s register
xxxx xxxx uuuu uuuu
0Bh,8Bh, INTCON
10Bh,18Bh
GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
81h,181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
85h
TRISA
—
— PORTA Data Direction Register
--11 1111 --11 1111
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by Timer0.
DS30275B-page 40
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