PIC16C77X
5.1.1 TIMER1 COUNTER OPERATION
In this mode, Timer1 is being incremented via an exter-
nal source. Increments occur on a rising edge. After
Timer1 is enabled in counter mode, the module must
first have a falling edge before the counter begins to
increment.
FIGURE 5-2: TIMER1 INCREMENTING EDGE
T1CKI
(Default high)
T1CKI
(Default low)
Note: Arrows indicate counter increments.
FIGURE 5-3: TIMER1 BLOCK DIAGRAM
Set flag bit
TMR1IF on
Overflow
RC0/T1OSO/T1CKI
RC1/T1OSI
TMR1
0
Synchronized
clock input
TMR1H TMR1L
1
T1OSC
TMR1ON
on/off
T1SYNC
T1OSCEN FOSC/4
Enable
Oscillator(1)
Internal
Clock
1
Prescaler
1, 2, 4, 8
0
2
T1CKPS1:T1CKPS0
Synchronize
det
SLEEP input
TMR1CS
Note 1: When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
DS30275B-page 42
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