PIC16LC773-I/SS View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC16LC773-I/SS

28/40-Pin, 8-Bit CMOS Microcontrollers w/ 12-Bit A/D

Microchip Technology 

PIC16C77X

8.2.5 MASTER MODE

Master mode of operation is supported by interrupt

generation on the detection of the START and STOP

conditions. The STOP (P) and START (S) bits are

cleared from a reset or when the MSSP module is dis-

abled. Control of the I2C bus may be taken when the P

bit is set, or the bus is idle with both the S and P bits

clear.

In master mode, the SCL and SDA lines are manipu-

lated by the MSSP hardware.

The following events will cause SSP Interrupt Flag bit,

SSPIF, to be set (SSP Interrupt if enabled):

• START condition

• STOP condition

• Data transfer byte transmitted/received

• Acknowledge transmit

• Repeated Start

FIGURE 8-17: SSP BLOCK DIAGRAM (I2C MASTER MODE)

SDA

SDA in

Read

Internal

data bus

Write

SSPBUF

SSPSR

MSb

shift

clock

LSb

SSPM3:SSPM0,

SSPADD<6:0>

Baud

rate

generator

SCL

Start bit, Stop bit,

Acknowledge

Generate

SCL in

Bus Collision

Start bit detect,

Stop bit detect

Write collision detect

Clock Arbitration

State counter for

end of XMIT/RCV

Set/Reset, S, P, WCOL (SSPSTAT)

Set SSPIF, BCLIF

Reset AKSTAT, PEN (SSPCON2)

 1999-2013 Microchip Technology Inc.

Advance Information

DS30275B-page 71

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