PIC16LC8X-04 View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC16LC8X-04

8-Bit CMOS EEPROM Microcontrollers

Microchip Technology 

8.5 Interrupts

The PIC16C8X group has 4 sources of interrupt:

• External interrupt RB0/INT pin

• TMR0 overflow interrupt

• PORTB change interrupts (pins RB7:RB4)

• EEPROM write complete interrupt

The interrupt control register (INTCON) records

individual interrupt requests in flag bits. It also contains

the individual and global interrupt enable bits.

The global interrupt enable bit, GIE (INTCON<7>)

enables (if set) all un-masked interrupts or disables (if

cleared) all interrupts. Individual interrupts can be

disabled through their corresponding enable bits in

INTCON register. Bit GIE is cleared on reset.

The “return from interrupt” instruction, RETFIE, exits

interrupt routine as well as sets the GIE bit, which

re-enable interrupts.

The RB0/INT pin interrupt, the RB port change interrupt

and the TMR0 overflow interrupt flags are contained in

the INTCON register.

PIC16C8X

When an interrupt is responded to; the GIE bit is

cleared to disable any further interrupt, the return

address is pushed onto the stack and the PC is loaded

with 0004h. For external interrupt events, such as the

RB0/INT pin or PORTB change interrupt, the interrupt

latency will be three to four instruction cycles. The

exact latency depends when the interrupt event occurs

(Figure 8-17). The latency is the same for both one and

two cycle instructions. Once in the interrupt service

routine the source(s) of the interrupt can be determined

by polling the interrupt flag bits. The interrupt flag bit(s)

must be cleared in software before re-enabling

interrupts to avoid infinite interrupt requests.

Note 1: Individual interrupt flag bits are set

regardless of the status of their

corresponding mask bit or the GIE bit.

Note 2: For the PIC16C84 Only;

If an interrupt occurs while the Global

Interrupt Enable (GIE) bit is being cleared,

the GIE bit may unintentionally be

re-enabled by the user’s Interrupt Service

Routine (the RETFIE instruction). The

events that would cause this to occur are:

1. An instruction clears the GIE bit while

an interrupt is acknowledged

2. The program branches to the

Interrupt vector and executes the

Interrupt Service Routine.

3. The Interrupt Service Routine

completes with the execution of the

RETFIE instruction. This causes the

GIE bit to be set (enables interrupts),

and the program returns to the

instruction after the one which was

meant to disable interrupts.

The method to ensure that interrupts are

globally disabled is:

1. Ensure that the GIE bit is cleared by

the instruction, as shown in the

following code:

LOOP

BCF INTCON,GIE ;Disable All

; Interrupts

BTFSC INTCON,GIE ;All Interrupts

; Disabled?

GOTO LOOP

;NO, try again

; Yes, continue

; with program

; flow

© 1995 Microchip Technology Inc.

DS30081F-page 47

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