PIC16LC8X View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC16LC8X

8-Bit CMOS EEPROM Microcontrollers

Microchip Technology 

8.8 Power-down Mode (SLEEP)

The Power-down mode is entered by executing the

SLEEP instruction.

If enabled, the Watchdog Timer will be cleared but

keeps running, the PD bit (STATUS<3>) is cleared, the

TO bit (STATUS<4>) is set, and the oscillator driver is

turned off. The I/O ports maintain the status they had,

before the SLEEP instruction was executed (driving

high, low, or hi-impedance).

For the lowest current consumption, in SLEEP mode,

place all I/O pins at either at VDD, or VSS, with no

external circuitry drawing current from the I/O pin, and

disable external clocks. I/O pins that are hi-impedance

inputs should be pulled high or low externally to avoid

switching currents caused by floating inputs. The

T0CKI input should also be at VDD or VSS. The

contribution from on-chip pull-ups on PORTB should

be considered.

The MCLR pin must be at a logic high level (VIHMC).

It should be noted that a RESET generated by a WDT

time-out does not drive the MCLR pin low.

8.8.1 WAKE-UP FROM SLEEP

The device can wake-up from SLEEP through one of

the following events:

1. External reset input on MCLR pin.

2. WDT Wake-up (if WDT was enabled).

3. Interrupt from RB0/INT pin, RB port change, or

data EEPROM write complete.

PIC16C8X

Peripherals cannot generate interrupts during SLEEP,

since no on-chip Q clocks are present.

The first event (MCLR reset) will cause a device reset.

The two latter events are considered a continuation of

program execution. The TO and PD bits can be used to

determine the cause of a device reset. The PD bit,

which is set on power-up, is cleared when SLEEP is

invoked. The TO bit is cleared if a WDT time-out

occurred (and caused wake-up).

While the SLEEP instruction is being executed, the next

instruction (PC + 1) is pre-fetched. For the device to

wake-up through an interrupt event, the corresponding

interrupt enable bit must be set (enabled). Wake-up

occurs regardless of the state of the GIE bit. If the GIE

bit is clear (disabled), the device continues execution at

the instruction after the SLEEP instruction. If the GIE bit

is set (enabled), the device executes the instruction

after the SLEEP instruction and then branches to the

interrupt address (0004h). In cases where the

execution of the instruction following SLEEP is not

desirable, the user should have a NOP after the

SLEEP instruction.

Note:

If global interrupts are disabled (GIE

cleared), but any interrupt source has both

its interrupt enable bit and corresponding

interrupt flag bits set, the device will

immediately wake from sleep. The SLEEP

instruction is completely executed.

The WDT is cleared when the device wakes-up from

sleep, regardless of the source of wake-up.

FIGURE 8-19: WAKE-UP FROM SLEEP THROUGH INTERRUPT

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1 (1)

CLKOUT(4)

tost(2)

INT pin

INTF flag

(INTCON<1>)

GIE bit

(INTCON<7>)

INSTRUCTION FLOW

Processor

in SLEEP

Interrupt Latency (2)

PC

PC

PC+1

PC+2

0004h (3)

0005h

Instruction

fetched

Instruction

executed

Inst (PC) = SLEEP

Inst (PC-1)

Inst (PC+1)

SLEEP

Inst (PC+2)

Inst (PC+1)

Dummy Cycle

Note 1: XT or LP oscillator mode assumed.

2: Tost = 1024Tosc (drawing not to scale). This delay will not be there for RC osc mode.

3: When GIE is set, processor jumps to interrupt routine after wake-up. If GIE is clear, execution will continue in-line.

4: CLKOUT is not available in these osc modes, but shown here for timing reference.

© 1995 Microchip Technology Inc.

DS30081F-page 51

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