PIC16CE624T-04SS View Datasheet(PDF) - Microchip Technology
Part Name
Description
Manufacturer
PIC16CE624T-04SS Datasheet PDF : 113 Pages
| |||
PIC16CE62X
BTFSS
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example
Bit Test f, Skip if Set
[ label ] BTFSS f,b
0 ≤ f ≤ 127
0≤b<7
skip if (f<b>) = 1
None
01 11bb bfff ffff
If bit ’b’ in register ’f’ is ’1’ then the next
instruction is skipped.
If bit ’b’ is ’1’, then the next instruction
fetched during the current instruction
execution, is discarded and a NOP is
executed instead, making this a
two-cycle instruction.
1
1(2)
HERE
FALSE
TRUE
BTFSS
GOTO
•
•
•
FLAG,1
PROCESS_CODE
Before Instruction
PC = address HERE
After Instruction
if FLAG<1> = 0,
PC = address FALSE
if FLAG<1> = 1,
PC = address TRUE
CALL
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example
Call Subroutine
[ label ] CALL k
0 ≤ k ≤ 2047
(PC)+ 1→ TOS,
k → PC<10:0>,
(PCLATH<4:3>) → PC<12:11>
None
10 0kkk kkkk kkkk
Call Subroutine. First, return address
(PC+1) is pushed onto the stack. The
eleven bit immediate address is
loaded into PC bits <10:0>. The upper
bits of the PC are loaded from
PCLATH. CALL is a two-cycle instruc-
tion.
1
2
HERE CALL THERE
Before Instruction
PC = Address HERE
After Instruction
PC = Address THERE
TOS = Address HERE+1
© 1999 Microchip Technology Inc.
CLRF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example
Clear f
[ label ] CLRF f
0 ≤ f ≤ 127
00h → (f)
1→Z
Z
00 0001 1fff ffff
The contents of register ’f’ are cleared
and the Z bit is set.
1
1
CLRF
FLAG_REG
Before Instruction
FLAG_REG = 0x5A
After Instruction
FLAG_REG = 0x00
Z
=1
CLRW
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example
Clear W
[ label ] CLRW
None
00h → (W)
1→Z
Z
00 0001 0000 0011
W register is cleared. Zero bit (Z) is
set.
1
1
CLRW
Before Instruction
W = 0x5A
After Instruction
W = 0x00
Z=1
DS40182C-page 69
Share Link: 