PIC16CE624T-04SS View Datasheet(PDF) - Microchip Technology
Part Name
Description
Manufacturer
PIC16CE624T-04SS Datasheet PDF : 113 Pages
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PIC16CE62X
SWAPF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example
Swap Nibbles in f
[ label ] SWAPF f,d
0 ≤ f ≤ 127
d ∈ [0,1]
(f<3:0>) → (dest<7:4>),
(f<7:4>) → (dest<3:0>)
None
00 1110 dfff ffff
The upper and lower nibbles of
register ’f’ are exchanged. If ’d’ is 0,
the result is placed in W register. If ’d’
is 1, the result is placed in register ’f’.
1
1
SWAPF REG, 0
Before Instruction
REG1 = 0xA5
After Instruction
REG1 = 0xA5
W
= 0x5A
XORLW
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Exclusive OR Literal with W
[ label ] XORLW k
0 ≤ k ≤ 255
(W) .XOR. k → (W)
Z
11 1010 kkkk kkkk
The contents of the W register are
XOR’ed with the eight bit literal 'k'.
The result is placed in the
W register.
1
1
XORLW 0xAF
Before Instruction
W = 0xB5
After Instruction
W = 0x1A
TRIS
Load TRIS Register
Syntax:
[ label ] TRIS f
Operands:
5≤f≤7
Operation:
(W) → TRIS register f;
Status Affected: None
Encoding:
00 0000 0110 0fff
Description:
The instruction is supported for code
compatibility with the PIC16C5X
products. Since TRIS registers are
readable and writable, the user can
directly address them.
Words:
1
Cycles:
1
Example
To maintain upward compatibility
with future PICmicro® products, do
not use this instruction.
XORWF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example
Exclusive OR W with f
[ label ] XORWF f,d
0 ≤ f ≤ 127
d ∈ [0,1]
(W) .XOR. (f) → (dest)
Z
00 0110 dfff ffff
Exclusive OR the contents of the
W register with register 'f'. If 'd' is 0,
the result is stored in the W register. If
'd' is 1, the result is stored back in reg-
ister 'f'.
1
1
XORWF REG 1
Before Instruction
REG
W
= 0xAF
= 0xB5
After Instruction
REG
W
= 0x1A
= 0xB5
DS40182C-page 76
© 1999 Microchip Technology Inc.
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