PIC12F/LF1822/16F/LF1823
FIGURE 18-2: COMPARATOR 1 MODULE SIMPLIFIED BLOCK DIAGRAM (PIC12F/LF1822)
CxNCH<1:0>
2
C1ON(1)
C1IN0-
C1IN1-
C1IN+
DAC
FVR Buffer2
VSS
0
MUX
(2)
1
0
MUX
1 (2)
2
3
C1VN -
+
C1VP
Cx(3)
C1HYS
C1SP
C1ON
C1PCH<1:0>
2
C1POL
Interrupt
det
C1INTP
Interrupt
det
C1INTN
Set C1IF
DQ
Q1 EN
C1OUT
MC1OUT
To Data Bus
To ECCP PWM Logic
C1SYNC
0
DQ
1
(from Timer1)
T1CLK
C1OE
TRIS bit
C1OUT
To Timer1 or SR Latch
SYNCC1OUT
Note 1:
2:
3:
When C1ON = 0, the Comparator will produce a ‘0’ at the output.
When C1ON = 0, all multiplexer inputs are disconnected.
Output of comparator can be frozen during debugging.
DS41413A-page 160
Preliminary
2010 Microchip Technology Inc.