PIC12F1822T-I/SL View Datasheet(PDF) - Microchip Technology
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Description
Manufacturer
PIC12F1822T-I/SL Datasheet PDF : 398 Pages
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PIC12F/LF1822/16F/LF1823
24.2.6 SPI OPERATION IN SLEEP MODE
In SPI Master mode, module clocks may be operating
at a different speed than when in full power mode; in
the case of the Sleep mode, all clocks are halted.
Special care must be taken by the user when the
MSSP1 clock is much faster than the system clock.
In Slave mode, when MSSP1 interrupts are enabled,
after the master completes sending data, an MSSP1
interrupt will wake the controller from Sleep.
If an exit from Sleep mode is not desired, MSSP1
interrupts should be disabled.
In SPI Master mode, when the Sleep mode is selected,
all module clocks are halted and the transmis-
sion/reception will remain in that state until the device
wakes. After the device returns to Run mode, the mod-
ule will resume transmitting and receiving data.
In SPI Slave mode, the SPI Transmit/Receive Shift
register operates asynchronously to the device. This
allows the device to be placed in Sleep mode and data
to be shifted into the SPI Transmit/Receive Shift
register. When all 8 bits have been received, the
MSSP1 interrupt flag bit will be set and if enabled, will
wake the device.
TABLE 24-1: SUMMARY OF REGISTERS ASSOCIATED WITH SPI OPERATION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
ANSELA
—
—
—
ANSA4
—
ANSA2 ANSA1 ANSA0
ANSELC
—
—
—
—
ANSC3
ANSC2 ANSC1 ANSC0
APFCON RXDTSEL SDOSEL SSSEL
—
T1GSEL TXCKSEL P1BSEL CCP1SEL
INTCON
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
PIE1
TMR1GIE ADIE
RCIE
TXIE
SSP1IE CCP1IE TMR2IE TMR1IE
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSP1IF CCP1IF TMR2IF TMR1IF
SSP1BUF Synchronous Serial Port Receive Buffer/Transmit Register
SSP1CON1 WCOL
SSPOV SSPEN
CKP
SSPM<3:0>
SSP1CON3 ACKTIM
PCIE
SCIE
BOEN
SDAHT
SBCDE
AHEN
DHEN
SSP1STAT SMP
CKE
D/A
P
S
R/W
UA
BF
TRISA
—
—
TRISA5 TRISA4
TRISA3
TRISA2 TRISA1 TRISA0
TRISC
—
—
TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0
Legend:
*
Note 1:
— = Unimplemented location, read as ‘0’. Shaded cells are not used by the MSSP1 in SPI mode.
Page provides register information.
PIC16F/LF1823 only.
122
126
118
89
90
92
229*
275
277
274
121
125
DS41413A-page 236
Preliminary
2010 Microchip Technology Inc.
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