TABLE 3-3: PIC12F/LF1822/PIC16F/LF1823 MEMORY MAP, BANKS 0-7
BANK0
BANK1
BANK2
BANK3
BANK4
000h
INDF0
080h
INDF0
100h
INDF0
180h
INDF0
200h
INDF0
001h
002h
INDF1
PCL
081h
082h
INDF1
PCL
101h
102h
INDF1
PCL
181h
182h
INDF1
PCL
201h
202h
INDF1
PCL
003h
004h
STATUS
FSR0L
083h
084h
STATUS
FSR0L
103h
104h
STATUS
FSR0L
183h
184h
STATUS
FSR0L
203h
204h
STATUS
FSR0L
005h
006h
FSR0H
FSR1L
085h
086h
FSR0H
FSR1L
105h
106h
FSR0H
FSR1L
185h
186h
FSR0H
FSR1L
205h
206h
FSR0H
FSR1L
007h
008h
FSR1H
BSR
087h
088h
FSR1H
BSR
107h
108h
FSR1H
BSR
187h
188h
FSR1H
BSR
207h
208h
FSR1H
BSR
009h
WREG
089h
WREG
109h
WREG
189h
WREG
209h
WREG
00Ah
00Bh
PCLATH
INTCON
08Ah
08Bh
PCLATH
INTCON
10Ah
10Bh
PCLATH
INTCON
18Ah
18Bh
PCLATH
INTCON
20Ah
20Bh
PCLATH
INTCON
00Ch
00Dh
00Eh
PORTA
—
PORTC(1)
08Ch
08Dh
08Eh
TRISA
—
TRISC(1)
10Ch
10Dh
10Eh
LATA
—
LATC(1)
18Ch
18Dh
18Eh
ANSELA
—
ANSELC(1)
20Ch
20Dh
20Eh
WPUA
—
WPUC(1)
00Fh
—
08Fh
—
10Fh
—
18Fh
—
20Fh
—
010h
—
090h
—
110h
—
190h
—
210h
—
011h
PIR1
091h
PIE1
111h CM1CON0 191h
EEADRL
211h
SSPBUF
012h
PIR2
092h
PIE2
112h CM1CON1 192h
EEADRH
212h
SSPADD
013h
—
093h
—
113h CM2CON0 193h
EEDATL
213h SSPMASK
014h
—
094h
—
114h CM2CON1 194h
EEDATH
214h SSPSTAT
015h
016h
017h
018h
019h
01Ah
01Bh
01Ch
TMR0
TMR1L
TMR1H
T1CON
T1GCON
TMR2
PR2
T2CON
095h
096h
097h
098h
099h
09Ah
09Bh
09Ch
OPTION
PCON
WDTCON
OSCTUNE
OSCCON
OSCSTAT
ADRESL
ADRESH
115h
116h
117h
118h
119h
11Ah
11Bh
11Ch
CMOUT
BORCON
FVRCON
DACCON0
DACCON1
SRCON0
SRCON1
—
195h
196h
197h
198h
199h
19Ah
19Bh
19Ch
EECON1
EECON2
—
—
RCREG
TXREG
SPBRGL
SPBRGH
215h
216h
217h
218h
219h
21Ah
21Bh
21Ch
SSPCON
SSPCON2
SSPCON3
—
—
—
—
—
01Dh
—
09Dh ADCON0 11Dh APFCON 19Dh
RCSTA
21Dh
—
01Eh CPSCON0 09Eh ADCON1 11Eh
—
19Eh
TXSTA
21Eh
—
01Fh
020h
06Fh
070h
CPSCON1
General
Purpose
Register
96 Bytes
09Fh
0A0h
0BFh
0EFh
0F0h
—
General
Purpose
Register
32 Bytes
Unimplemented
Read as ‘0’
11Fh
120h
16Fh
170h
—
Unimplemented
Read as ‘0’
19Fh
1A0h
1EFh
1F0h
BAUDCON
Unimplemented
Read as ‘0’
21Fh
220h
26Fh
270h
—
Unimplemented
Read as ‘0’
Accesses
70h – 7Fh
Accesses
70h – 7Fh
Accesses
70h – 7Fh
Accesses
70h – 7Fh
07Fh
0FFh
17Fh
1FFh
27Fh
280h
281h
282h
283h
284h
285h
286h
287h
288h
289h
28Ah
28Bh
28Ch
28Dh
28Eh
28Fh
290h
291h
292h
293h
294h
295h
296h
297h
298h
299h
29Ah
29Bh
29Ch
29Dh
29Eh
29Fh
2A0h
2EFh
2F0h
2FFh
BANK5
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
—
—
—
—
—
CCPR1L
CCPR1H
CCP1CON
PWM1CON
CCP1AS
PSTR1CON
—
—
—
—
—
—
—
—
—
Unimplemented
Read as ‘0’
Accesses
70h – 7Fh
300h
301h
302h
303h
304h
305h
306h
307h
308h
309h
30Ah
30Bh
30Ch
30Dh
30Eh
30Fh
310h
311h
312h
313h
314h
315h
316h
317h
318h
319h
31Ah
31Bh
31Ch
31Dh
31Eh
31Fh
320h
36Fh
370h
37Fh
BANK6
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Unimplemented
Read as ‘0’
Accesses
70h – 7Fh
380h
381h
382h
383h
384h
385h
386h
387h
388h
389h
38Ah
38Bh
38Ch
38Dh
38Eh
38Fh
390h
391h
392h
393h
394h
395h
396h
397h
398h
399h
39Ah
39Bh
39Ch
39Dh
39Eh
39Fh
3A0h
3EFh
3F0h
3FFh
BANK7
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
—
—
—
—
—
IOCAP
IOCAN
IOCAF
—
—
—
—
—
—
CLKRCON
—
MDCON
MDSRC
MDCARL
MDCARH
Unimplemented
Read as ‘0’
Accesses
70h – 7Fh
Legend:
Note 1:
= Unimplemented data memory locations, read as ‘0’
Available only on PIC16F/LF1823.