PIC12F1822T-I/SL View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC12F1822T-I/SL

8/14-Pin Flash Microcontrollers with nanoWatt XLP Technology

Microchip Technology 

PIC12F/LF1822/16F/LF1823

FIGURE 25-12: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)

RX/DT

pin

TX/CK pin

(SCKP = 0)

bit 0

bit 1

bit 2

bit 3

bit 4

bit 5

bit 6

bit 7

TX/CK pin

(SCKP = 1)

Write to

bit SREN

SREN bit

CREN bit ‘0’

‘0’

RCIF bit

(Interrupt)

Read

RCREG

Note:

Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.

TABLE 25-8: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER

RECEPTION

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Register

on Page

BAUDCON ABDOVF RCIDL

—

SCKP BRG16

—

WUE ABDEN

290

INTCON

GIE

PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF

89

PIE1

PIR1

RCREG

TMR1GIE ADIE

TMR1GIF ADIF

RCIE

TXIE SSP1IE CCP1IE

RCIF

TXIF SSP1IF CCP1IF

EUSART Receive Data Register

TMR2IE

TMR2IF

TMR1IE

TMR1IF

90

92

284*

RCSTA

SPEN

RX9

SREN CREN ADDEN FERR OERR RX9D

289

SPBRGL

BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0

291*

SPBRGH

TRISC(1)

BRG15

—

BRG14 BRG13 BRG12 BRG11 BRG10 BRG9 BRG8

—

TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0

291*

125

TXSTA

CSRC

TX9

TXEN SYNC SENDB BRGH TRMT TX9D

288

Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for Synchronous Master Reception.

* Page provides register information.

Note 1: PIC16F/LF1823 only.

 2010 Microchip Technology Inc.

Preliminary

DS41413A-page 303

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