PIC12F1822T-I/SL View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC12F1822T-I/SL

8/14-Pin Flash Microcontrollers with nanoWatt XLP Technology

Microchip Technology 

PIC12F/LF1822/16F/LF1823

TMR1H Register ....................................................... 172

TMR1L Register ........................................................ 172

Timer2 ............................................................................... 184

Associated registers.................................................. 187

Timer2/4/6

Associated registers.................................................. 187

Timers

Timer1

T1CON.............................................................. 180

T1GCON ........................................................... 181

Timer2

T2CON.............................................................. 186

Timing Diagrams

A/D Conversion ......................................................... 356

A/D Conversion (Sleep Mode) .................................. 356

Acknowledge Sequence ........................................... 265

Asynchronous Reception .......................................... 286

Asynchronous Transmission ..................................... 282

Asynchronous Transmission (Back to Back) ............ 282

Auto Wake-up Bit (WUE) During Normal Operation . 298

Auto Wake-up Bit (WUE) During Sleep .................... 298

Automatic Baud Rate Calibration .............................. 296

Baud Rate Generator with Clock Arbitration ............. 258

BRG Reset Due to SDA Arbitration During Start

Condition........................................................... 269

Brown-out Reset (BOR) ............................................ 352

Brown-out Reset Situations ........................................ 77

Bus Collision During a Repeated Start Condition

(Case 1) ............................................................ 270

Bus Collision During a Repeated Start Condition

(Case 2) ............................................................ 270

Bus Collision During a Start Condition (SCL = 0) ..... 269

Bus Collision During a Stop Condition (Case 1) ....... 271

Bus Collision During a Stop Condition (Case 2) ....... 271

Bus Collision During Start Condition (SDA only) ...... 268

Bus Collision for Transmit and Acknowledge............ 267

CLKOUT and I/O....................................................... 350

Clock Synchronization .............................................. 255

Clock Timing ............................................................. 348

Comparator Output ................................................... 159

Enhanced Capture/Compare/PWM (ECCP) ............. 354

Fail-Safe Clock Monitor (FSCM) ................................. 67

First Start Bit Timing ................................................. 259

Full-Bridge PWM Output ........................................... 213

Half-Bridge PWM Output .................................. 211, 217

I2C Bus Data ............................................................. 362

I2C Bus Start/Stop Bits.............................................. 361

I2C Master Mode (7 or 10-Bit Transmission) ............ 262

I2C Master Mode (7-Bit Reception) ........................... 264

I2C Stop Condition Receive or Transmit Mode ......... 266

INT Pin Interrupt.......................................................... 87

Internal Oscillator Switch Timing................................. 62

PWM Auto-shutdown ................................................ 216

Firmware Restart .............................................. 216

PWM Direction Change ............................................ 214

PWM Direction Change at Near 100% Duty Cycle ... 215

PWM Output (Active-High)........................................ 209

PWM Output (Active-Low) ........................................ 210

Repeat Start Condition.............................................. 260

Reset Start-up Sequence............................................ 79

Reset, WDT, OST and Power-up Timer ................... 351

Send Break Character Sequence ............................. 299

SPI Master Mode (CKE = 1, SMP = 1) ..................... 359

SPI Mode (Master Mode) .......................................... 232

SPI Slave Mode (CKE = 0) ....................................... 360

SPI Slave Mode (CKE = 1) ....................................... 360

Synchronous Reception (Master Mode, SREN) ....... 303

Synchronous Transmission ...................................... 301

Synchronous Transmission (Through TXEN) ........... 301

Timer0 and Timer1 External Clock ........................... 353

Timer1 Incrementing Edge ....................................... 176

Two Speed Start-up.................................................... 65

USART Synchronous Receive (Master/Slave) ......... 358

USART Synchronous Transmission

(Master/Slave) .................................................. 358

Wake-up from Interrupt............................................... 96

Timing Diagrams and Specifications

PLL Clock ................................................................. 349

Timing Parameter Symbology .......................................... 347

Timing Requirements

I2C Bus Data............................................................. 363

SPI Mode .................................................................. 361

TMR0 Register.................................................................... 31

TMR1H Register ................................................................. 31

TMR1L Register.................................................................. 31

TMR2 Register.................................................................... 31

TRIS.................................................................................. 332

TRISA Register........................................................... 32, 121

TRISC Register........................................................... 32, 125

Two-Speed Clock Start-up Mode........................................ 64

TXREG ............................................................................. 281

TXREG Register ................................................................. 34

TXSTA Register.......................................................... 34, 288

BRGH Bit .................................................................. 291

U

USART

Synchronous Master Mode

Requirements, Synchronous Receive .............. 358

Requirements, Synchronous Transmission...... 358

Timing Diagram, Synchronous Receive ........... 358

Timing Diagram, Synchronous Transmission... 358

V

VREF. SEE ADC Reference Voltage

W

Wake-up on Break ............................................................ 297

Wake-up Using Interrupts ................................................... 96

Watchdog Timer (WDT)...................................................... 78

Modes ....................................................................... 100

Specifications ........................................................... 353

WCOL ....................................................... 258, 261, 263, 265

WCOL Status Flag.................................... 258, 261, 263, 265

WDTCON Register ........................................................... 101

WPUB Register................................................................. 123

WPUC Register ................................................................ 126

Write Protection .................................................................. 53

WWW Address ................................................................. 395

WWW, On-Line Support ..................................................... 10

DS41413A-page 394

Preliminary

 2010 Microchip Technology Inc.

Share Link: