PIC16F1828T-I/SL View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC16F1828T-I/SL

28/40/44-Pin, Low-Power, High-Performance Microcontrollers with nanoWatt XLP Technology

Microchip Technology 

PIC16(L)F1824/1828

17.4 Low Power Voltage State

In order for the DAC module to consume the least

amount of power, one of the two voltage reference input

sources to the resistor ladder must be disconnected.

Either the positive voltage source, (VSRC+), or the

negative voltage source, (VSRC-) can be disabled.

The negative voltage source is disabled by setting the

DACLPS bit in the DACCON0 register. Clearing the

DACLPS bit in the DACCON0 register disables the

positive voltage source.

17.4.1

OUTPUT CLAMPED TO POSITIVE

VOLTAGE SOURCE

The DAC output voltage can be set to VSRC+ with the

least amount of power consumption by performing the

following:

• Clearing the DACEN bit in the DACCON0 register.

• Setting the DACLPS bit in the DACCON0 register.

• Configuring the DACPSS bits to the proper

positive source.

• Configuring the DACR<4:0> bits to ‘11111’ in the

DACCON1 register.

This is also the method used to output the voltage level

from the FVR to an output pin. See Section FIGURE

17-2: “Voltage Reference Output Buffer Example”

for more information.

Reference Figure 17-3 for output clamping examples.

17.4.2

OUTPUT CLAMPED TO NEGATIVE

VOLTAGE SOURCE

The DAC output voltage can be set to VSRC- with the

least amount of power consumption by performing the

following:

• Clearing the DACEN bit in the DACCON0 register.

• Clearing the DACLPS bit in the DACCON0 register.

• Configuring the DACNSS bits to the proper

negative source.

• Configuring the DACR<4:0> bits to ‘00000’ in the

DACCON1 register.

This allows the comparator to detect a zero-crossing

while not consuming additional current through the DAC

module.

Reference Figure 17-3 for output clamping examples.

FIGURE 17-3:

OUTPUT VOLTAGE CLAMPING EXAMPLES

Output Clamped to Positive Voltage Source

Output Clamped to Negative Voltage Source

VSRC+

DACEN = 0

DACLPS = 1

VSRC-

R DACR<4:0> = 11111

R

DAC Voltage Ladder

(see Figure 17-1)

R

VSRC+

DACEN = 0

DACLPS = 0

VSRC-

R

R

DAC Voltage Ladder

(see Figure 17-1)

R DACR<4:0> = 00000

17.5 Operation During Sleep

When the device wakes up from Sleep through an

interrupt or a Watchdog Timer time-out, the contents of

the DACCON0 register are not affected. To minimize

current consumption in Sleep mode, the voltage

reference should be disabled.

17.6 Effects of a Reset

A device Reset affects the following:

• DAC is disabled.

• DAC output voltage is removed from the

DACOUT pin.

• The DACR<4:0> range select bits are cleared.

 2010 Microchip Technology Inc.

Preliminary

DS41419B-page 165

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